Searched refs:SOR_REFCLK_DIV_INT (Results 1 – 4 of 4) sorted by relevance
387 #define SOR_REFCLK_DIV_INT(x) ((((x) >> 2) & 0xff) << 8) macro
405 #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8) macro
1260 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82); in tegra_hdmi_encoder_enable()
2550 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); in tegra_sor_hdmi_enable()