Searched refs:SOR_PWM_CTL_CLK_SEL (Results 1 – 2 of 2) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/tegra/ | ||
| D | sor.h | 195 #define SOR_PWM_CTL_CLK_SEL (1 << 30) macro |
| D | sor.c | 732 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm() |