Searched refs:SOR_LANE_SEQ_CTL_POWER_STATE_UP (Results 1 – 2 of 2) sorted by relevance
160 #define SOR_LANE_SEQ_CTL_POWER_STATE_UP (0 << 16) macro
1857 SOR_LANE_SEQ_CTL_POWER_STATE_UP; in tegra_sor_edp_enable()2498 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); in tegra_sor_hdmi_enable()
