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Searched refs:SOC15_WAIT_ON_RREG (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c676 SOC15_WAIT_ON_RREG(VCN, 0, in jpeg_v2_0_start()
770 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, in jpeg_v2_0_stop()
859 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, in vcn_v2_0_disable_static_power_gating()
873 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret); in vcn_v2_0_disable_static_power_gating()
924 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret); in vcn_v2_0_enable_static_power_gating()
1233 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1238 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); in vcn_v2_0_stop_dpg_mode()
1241 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); in vcn_v2_0_stop_dpg_mode()
1244 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); in vcn_v2_0_stop_dpg_mode()
1247 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); in vcn_v2_0_stop_dpg_mode()
[all …]
Dvcn_v1_0.c706 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); in vcn_1_0_disable_static_power_gating()
720 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); in vcn_1_0_disable_static_power_gating()
771 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); in vcn_1_0_enable_static_power_gating()
1143 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); in vcn_v1_0_stop_spg_mode()
1149 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); in vcn_v1_0_stop_spg_mode()
1158 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); in vcn_v1_0_stop_spg_mode()
1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1192 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); in vcn_v1_0_stop_dpg_mode()
1195 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); in vcn_v1_0_stop_dpg_mode()
1198 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); in vcn_v1_0_stop_dpg_mode()
[all …]
Dvcn_v2_5.c473 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, ret); in vcn_v2_5_disable_clock_gating()
901 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); in vcn_v2_5_stop()
909 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r); in vcn_v2_5_stop()
920 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r); in vcn_v2_5_stop()
1274 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle()
Dsoc15_common.h50 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \ macro