Searched refs:SIMD (Results 1 – 8 of 8) sorted by relevance
84 uint32_t SIMD:2; /* SIMD id */ member
507 reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD; in dbgdev_wave_control_set_registers()
483 * All SVE register bits that are not shared with FP/SIMD are caller-save.491 Appendix B. ARMv8-A FP/SIMD programmer's model499 ARMv8-A defines the following floating-point / SIMD register state:
310 bool "Support SIMD acceleration for AEGIS-128"704 in IETF protocols. This is the x86_64 assembler implementation using SIMD878 using powerpc SPE SIMD instruction set.903 implemented using powerpc SPE SIMD instruction set.
2496 bool "Support for the MIPS SIMD Architecture"2501 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers2502 and a set of SIMD instructions to operate on them. When this option
2056 bool "Advanced SIMD (NEON) Extension support"2059 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1447 execution state which complements and extends the SIMD functionality
2136 arm64 core/FP-SIMD registers have the following id bit patterns. Note2269 if the guest FPU mode is changed. MIPS SIMD Architecture (MSA) vector4685 This capability allows the use of the MIPS SIMD Architecture (MSA) by the guest.
