1 /* SPDX-License-Identifier: GPL-2.0-or-later 2 * Aquantia Corp. Aquantia AQtion USB to 5GbE Controller 3 * Copyright (C) 2003-2005 David Hollis <dhollis@davehollis.com> 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> 5 * Copyright (C) 2002-2003 TiVo Inc. 6 * Copyright (C) 2017-2018 ASIX 7 * Copyright (C) 2018 Aquantia Corp. 8 */ 9 10 #ifndef __LINUX_USBNET_AQC111_H 11 #define __LINUX_USBNET_AQC111_H 12 13 #define URB_SIZE (1024 * 62) 14 15 #define AQ_MCAST_FILTER_SIZE 8 16 #define AQ_MAX_MCAST 64 17 18 #define AQ_ACCESS_MAC 0x01 19 #define AQ_FLASH_PARAMETERS 0x20 20 #define AQ_PHY_POWER 0x31 21 #define AQ_WOL_CFG 0x60 22 #define AQ_PHY_OPS 0x61 23 24 #define AQ_USB_PHY_SET_TIMEOUT 10000 25 #define AQ_USB_SET_TIMEOUT 4000 26 27 /* Feature. ********************************************/ 28 #define AQ_SUPPORT_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\ 29 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\ 30 NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_TX |\ 31 NETIF_F_HW_VLAN_CTAG_RX) 32 33 #define AQ_SUPPORT_HW_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\ 34 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\ 35 NETIF_F_TSO | NETIF_F_HW_VLAN_CTAG_FILTER) 36 37 #define AQ_SUPPORT_VLAN_FEATURE (NETIF_F_SG | NETIF_F_IP_CSUM |\ 38 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |\ 39 NETIF_F_TSO) 40 41 /* SFR Reg. ********************************************/ 42 43 #define SFR_GENERAL_STATUS 0x03 44 #define SFR_CHIP_STATUS 0x05 45 #define SFR_RX_CTL 0x0B 46 #define SFR_RX_CTL_TXPADCRC 0x0400 47 #define SFR_RX_CTL_IPE 0x0200 48 #define SFR_RX_CTL_DROPCRCERR 0x0100 49 #define SFR_RX_CTL_START 0x0080 50 #define SFR_RX_CTL_RF_WAK 0x0040 51 #define SFR_RX_CTL_AP 0x0020 52 #define SFR_RX_CTL_AM 0x0010 53 #define SFR_RX_CTL_AB 0x0008 54 #define SFR_RX_CTL_AMALL 0x0002 55 #define SFR_RX_CTL_PRO 0x0001 56 #define SFR_RX_CTL_STOP 0x0000 57 #define SFR_INTER_PACKET_GAP_0 0x0D 58 #define SFR_NODE_ID 0x10 59 #define SFR_MULTI_FILTER_ARRY 0x16 60 #define SFR_MEDIUM_STATUS_MODE 0x22 61 #define SFR_MEDIUM_XGMIIMODE 0x0001 62 #define SFR_MEDIUM_FULL_DUPLEX 0x0002 63 #define SFR_MEDIUM_RXFLOW_CTRLEN 0x0010 64 #define SFR_MEDIUM_TXFLOW_CTRLEN 0x0020 65 #define SFR_MEDIUM_JUMBO_EN 0x0040 66 #define SFR_MEDIUM_RECEIVE_EN 0x0100 67 #define SFR_MONITOR_MODE 0x24 68 #define SFR_MONITOR_MODE_EPHYRW 0x01 69 #define SFR_MONITOR_MODE_RWLC 0x02 70 #define SFR_MONITOR_MODE_RWMP 0x04 71 #define SFR_MONITOR_MODE_RWWF 0x08 72 #define SFR_MONITOR_MODE_RW_FLAG 0x10 73 #define SFR_MONITOR_MODE_PMEPOL 0x20 74 #define SFR_MONITOR_MODE_PMETYPE 0x40 75 #define SFR_PHYPWR_RSTCTL 0x26 76 #define SFR_PHYPWR_RSTCTL_BZ 0x0010 77 #define SFR_PHYPWR_RSTCTL_IPRL 0x0020 78 #define SFR_VLAN_ID_ADDRESS 0x2A 79 #define SFR_VLAN_ID_CONTROL 0x2B 80 #define SFR_VLAN_CONTROL_WE 0x0001 81 #define SFR_VLAN_CONTROL_RD 0x0002 82 #define SFR_VLAN_CONTROL_VSO 0x0010 83 #define SFR_VLAN_CONTROL_VFE 0x0020 84 #define SFR_VLAN_ID_DATA0 0x2C 85 #define SFR_VLAN_ID_DATA1 0x2D 86 #define SFR_RX_BULKIN_QCTRL 0x2E 87 #define SFR_RX_BULKIN_QCTRL_TIME 0x01 88 #define SFR_RX_BULKIN_QCTRL_IFG 0x02 89 #define SFR_RX_BULKIN_QCTRL_SIZE 0x04 90 #define SFR_RX_BULKIN_QTIMR_LOW 0x2F 91 #define SFR_RX_BULKIN_QTIMR_HIGH 0x30 92 #define SFR_RX_BULKIN_QSIZE 0x31 93 #define SFR_RX_BULKIN_QIFG 0x32 94 #define SFR_RXCOE_CTL 0x34 95 #define SFR_RXCOE_IP 0x01 96 #define SFR_RXCOE_TCP 0x02 97 #define SFR_RXCOE_UDP 0x04 98 #define SFR_RXCOE_ICMP 0x08 99 #define SFR_RXCOE_IGMP 0x10 100 #define SFR_RXCOE_TCPV6 0x20 101 #define SFR_RXCOE_UDPV6 0x40 102 #define SFR_RXCOE_ICMV6 0x80 103 #define SFR_TXCOE_CTL 0x35 104 #define SFR_TXCOE_IP 0x01 105 #define SFR_TXCOE_TCP 0x02 106 #define SFR_TXCOE_UDP 0x04 107 #define SFR_TXCOE_ICMP 0x08 108 #define SFR_TXCOE_IGMP 0x10 109 #define SFR_TXCOE_TCPV6 0x20 110 #define SFR_TXCOE_UDPV6 0x40 111 #define SFR_TXCOE_ICMV6 0x80 112 #define SFR_BM_INT_MASK 0x41 113 #define SFR_BMRX_DMA_CONTROL 0x43 114 #define SFR_BMRX_DMA_EN 0x80 115 #define SFR_BMTX_DMA_CONTROL 0x46 116 #define SFR_PAUSE_WATERLVL_LOW 0x54 117 #define SFR_PAUSE_WATERLVL_HIGH 0x55 118 #define SFR_ARC_CTRL 0x9E 119 #define SFR_SWP_CTRL 0xB1 120 #define SFR_TX_PAUSE_RESEND_T 0xB2 121 #define SFR_ETH_MAC_PATH 0xB7 122 #define SFR_RX_PATH_READY 0x01 123 #define SFR_BULK_OUT_CTRL 0xB9 124 #define SFR_BULK_OUT_FLUSH_EN 0x01 125 #define SFR_BULK_OUT_EFF_EN 0x02 126 127 #define AQ_FW_VER_MAJOR 0xDA 128 #define AQ_FW_VER_MINOR 0xDB 129 #define AQ_FW_VER_REV 0xDC 130 131 /*PHY_OPS**********************************************************************/ 132 133 #define AQ_ADV_100M BIT(0) 134 #define AQ_ADV_1G BIT(1) 135 #define AQ_ADV_2G5 BIT(2) 136 #define AQ_ADV_5G BIT(3) 137 #define AQ_ADV_MASK 0x0F 138 139 #define AQ_PAUSE BIT(16) 140 #define AQ_ASYM_PAUSE BIT(17) 141 #define AQ_LOW_POWER BIT(18) 142 #define AQ_PHY_POWER_EN BIT(19) 143 #define AQ_WOL BIT(20) 144 #define AQ_DOWNSHIFT BIT(21) 145 146 #define AQ_DSH_RETRIES_SHIFT 0x18 147 #define AQ_DSH_RETRIES_MASK 0xF000000 148 149 #define AQ_WOL_FLAG_MP 0x2 150 151 /******************************************************************************/ 152 153 struct aqc111_wol_cfg { 154 u8 hw_addr[6]; 155 u8 flags; 156 u8 rsvd[283]; 157 } __packed; 158 159 #define WOL_CFG_SIZE sizeof(struct aqc111_wol_cfg) 160 161 struct aqc111_data { 162 u16 rxctl; 163 u8 rx_checksum; 164 u8 link_speed; 165 u8 link; 166 u8 autoneg; 167 u32 advertised_speed; 168 struct { 169 u8 major; 170 u8 minor; 171 u8 rev; 172 } fw_ver; 173 u32 phy_cfg; 174 u8 wol_flags; 175 }; 176 177 #define AQ_LS_MASK 0x8000 178 #define AQ_SPEED_MASK 0x7F00 179 #define AQ_SPEED_SHIFT 0x0008 180 #define AQ_INT_SPEED_5G 0x000F 181 #define AQ_INT_SPEED_2_5G 0x0010 182 #define AQ_INT_SPEED_1G 0x0011 183 #define AQ_INT_SPEED_100M 0x0013 184 185 /* TX Descriptor */ 186 #define AQ_TX_DESC_LEN_MASK 0x1FFFFF 187 #define AQ_TX_DESC_DROP_PADD BIT(28) 188 #define AQ_TX_DESC_VLAN BIT(29) 189 #define AQ_TX_DESC_MSS_MASK 0x7FFF 190 #define AQ_TX_DESC_MSS_SHIFT 0x20 191 #define AQ_TX_DESC_VLAN_MASK 0xFFFF 192 #define AQ_TX_DESC_VLAN_SHIFT 0x30 193 194 #define AQ_RX_HW_PAD 0x02 195 196 /* RX Packet Descriptor */ 197 #define AQ_RX_PD_L4_ERR BIT(0) 198 #define AQ_RX_PD_L3_ERR BIT(1) 199 #define AQ_RX_PD_L4_TYPE_MASK 0x1C 200 #define AQ_RX_PD_L4_UDP 0x04 201 #define AQ_RX_PD_L4_TCP 0x10 202 #define AQ_RX_PD_L3_TYPE_MASK 0x60 203 #define AQ_RX_PD_L3_IP 0x20 204 #define AQ_RX_PD_L3_IP6 0x40 205 206 #define AQ_RX_PD_VLAN BIT(10) 207 #define AQ_RX_PD_RX_OK BIT(11) 208 #define AQ_RX_PD_DROP BIT(31) 209 #define AQ_RX_PD_LEN_MASK 0x7FFF0000 210 #define AQ_RX_PD_LEN_SHIFT 0x10 211 #define AQ_RX_PD_VLAN_SHIFT 0x20 212 213 /* RX Descriptor header */ 214 #define AQ_RX_DH_PKT_CNT_MASK 0x1FFF 215 #define AQ_RX_DH_DESC_OFFSET_MASK 0xFFFFE000 216 #define AQ_RX_DH_DESC_OFFSET_SHIFT 0x0D 217 218 static struct { 219 unsigned char ctrl; 220 unsigned char timer_l; 221 unsigned char timer_h; 222 unsigned char size; 223 unsigned char ifg; 224 } AQC111_BULKIN_SIZE[] = { 225 /* xHCI & EHCI & OHCI */ 226 {7, 0x00, 0x01, 0x1E, 0xFF},/* 10G, 5G, 2.5G, 1G */ 227 {7, 0xA0, 0x00, 0x14, 0x00},/* 100M */ 228 /* Jumbo packet */ 229 {7, 0x00, 0x01, 0x18, 0xFF}, 230 }; 231 232 #endif /* __LINUX_USBNET_AQC111_H */ 233
