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Searched refs:SDMA0_PHASE0_QUANTUM__VALUE_MASK (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dcik_sdma.c356 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in cik_ctx_switch_enable()
363 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in cik_ctx_switch_enable()
Dsdma_v3_0.c565 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v3_0_ctx_switch_enable()
572 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v3_0_ctx_switch_enable()
Dsdma_v5_0.c532 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v5_0_ctx_switch_enable()
539 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v5_0_ctx_switch_enable()
Dsdma_v4_0.c896 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v4_0_ctx_switch_enable()
903 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v4_0_ctx_switch_enable()
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_sh_mask.h599 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro
Dsdma0_4_0_sh_mask.h600 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L macro
Dsdma0_4_2_2_sh_mask.h608 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro
Dsdma0_4_2_sh_mask.h602 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_0_sh_mask.h1013 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
Doss_2_4_sh_mask.h1103 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
Doss_3_0_1_sh_mask.h1123 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
Doss_3_0_sh_mask.h1629 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
/Linux-v5.4/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_sh_mask.h314 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro