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Searched refs:SCLK_TIMER0 (Results 1 – 20 of 20) sorted by relevance

/Linux-v5.4/include/dt-bindings/clock/
Drk3036-cru.h28 #define SCLK_TIMER0 85 macro
Drk3188-cru-common.h40 #define SCLK_TIMER0 84 macro
Drk3128-cru.h31 #define SCLK_TIMER0 85 macro
Drk3228-cru.h31 #define SCLK_TIMER0 85 macro
Drv1108-cru.h28 #define SCLK_TIMER0 78 macro
Dpx30-cru.h40 #define SCLK_TIMER0 38 macro
Drk3288-cru.h40 #define SCLK_TIMER0 85 macro
Drk3308-cru.h34 #define SCLK_TIMER0 30 macro
Drk3328-cru.h36 #define SCLK_TIMER0 47 macro
/Linux-v5.4/drivers/clk/rockchip/
Dclk-rk3036.c224 COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
Dclk-rk3128.c296 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
Dclk-rk3228.c355 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
Dclk-rv1108.c554 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
Dclk-rk3188.c439 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
Dclk-rk3328.c477 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
Dclk-rk3288.c391 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
Dclk-px30.c714 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
Dclk-rk3308.c413 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
/Linux-v5.4/arch/arm/boot/dts/
Drk3066a.dtsi251 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
/Linux-v5.4/arch/arm64/boot/dts/rockchip/
Dpx30.dtsi641 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;