Searched refs:SCLK_I2S0 (Results 1 – 22 of 22) sorted by relevance
| /Linux-v5.4/include/dt-bindings/clock/ |
| D | s3c2443.h | 32 #define SCLK_I2S0 18 macro
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| D | rk3188-cru-common.h | 31 #define SCLK_I2S0 75 macro
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| D | rk3128-cru.h | 28 #define SCLK_I2S0 80 macro
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| D | rk3228-cru.h | 27 #define SCLK_I2S0 80 macro
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| D | rv1108-cru.h | 25 #define SCLK_I2S0 75 macro
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| D | rk3288-cru.h | 37 #define SCLK_I2S0 82 macro
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| D | rk3328-cru.h | 30 #define SCLK_I2S0 41 macro
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| /Linux-v5.4/drivers/clk/samsung/ |
| D | clk-s3c2443.c | 114 GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
173 ALIAS(SCLK_I2S0, NULL, "i2s-if"),
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| /Linux-v5.4/Documentation/devicetree/bindings/sound/ |
| D | rockchip-i2s.txt | 46 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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| /Linux-v5.4/drivers/clk/rockchip/ |
| D | clk-rk3188.c | 546 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
670 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3128.c | 363 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
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| D | clk-rk3228.c | 425 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
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| D | clk-rv1108.c | 507 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
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| D | clk-rk3328.c | 376 GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
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| D | clk-rk3288.c | 364 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | rk3288-firefly-reload.dts | 222 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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| D | rk3188-bqedison2qc.dts | 439 clocks = <&cru SCLK_I2S0>;
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| D | rk3066a.dtsi | 166 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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| D | rk3188.dtsi | 176 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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| D | rk322x.dtsi | 173 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
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| D | rk3288.dtsi | 970 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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| /Linux-v5.4/arch/arm64/boot/dts/rockchip/ |
| D | rk3328.dtsi | 183 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
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