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Searched refs:RT (Results 1 – 25 of 45) sorted by relevance

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/Linux-v5.4/arch/mips/mm/
Duasm-mips.c51 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
52 [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
53 [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
54 [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
55 [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
56 [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
57 [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
58 [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
65 [insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
68 [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
[all …]
Duasm-micromips.c43 [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
44 [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
45 [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
46 [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
47 [insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
53 [insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
54 [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
55 [insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
57 [insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},
62 [insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS},
[all …]
/Linux-v5.4/arch/powerpc/crypto/
Dsha1-powerpc-asm.S26 #define RT(t) ((((t)+5)%6)+7) macro
42 rotlwi RT(t),RA(t),5; \
45 add RT(t),RT(t),r6; \
49 add RT(t),RT(t),r14
54 rotlwi RT(t),RA(t),5; \
59 add RT(t),RT(t),r6; \
63 add RT(t),RT(t),r0; \
68 rotlwi RT(t),RA(t),5; \
72 add RT(t),RT(t),r6; \
74 add RT(t),RT(t),r0
[all …]
/Linux-v5.4/arch/powerpc/xmon/
Dppc-opc.c566 #define RT RS macro
3101 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3102 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3108 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3110 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3142 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3144 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3147 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3177 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3179 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dst-pincfg.h20 #define RT (1 << 23) macro
51 #define SE_NICLK_IO (RT)
56 #define SE_ICLK_IO (RT | INVERTCLK)
61 #define DE_IO (RT | DOUBLE_EDGE)
66 #define ICLK (RT | CLKNOTDATA | INVERTCLK)
71 #define NICLK (RT | CLKNOTDATA)
Dbcm4708-asus-rt-ac68u.dts4 * DTS for Asus RT-AC68U
16 model = "Asus RT-AC68U (BCM4708)";
Dbcm47081-asus-rt-n18u.dts4 * DTS for Asus RT-N18U
16 model = "Asus RT-N18U (BCM47081)";
Dbcm4708-asus-rt-ac56u.dts4 * DTS for Asus RT-AC56U
16 model = "Asus RT-AC56U (BCM4708)";
Dbcm4709-asus-rt-ac87u.dts4 * DTS for Asus RT-AC87U
16 model = "Asus RT-AC87U";
/Linux-v5.4/drivers/media/platform/rockchip/rga/
Drga-hw.c15 RT = 2, enumerator
92 LT, RT, LB, RB, in rga_lookup_draw_pos()
95 RT, LT, RB, LB, in rga_lookup_draw_pos()
98 RB, LB, RT, LT, in rga_lookup_draw_pos()
101 LB, RB, LT, RT, in rga_lookup_draw_pos()
113 case RT: in rga_lookup_draw_pos()
/Linux-v5.4/arch/x86/crypto/
Dtwofish-avx-x86_64-asm_64.S61 #define RT %xmm14 macro
146 vpaddd x, RK1, RT;\
148 vpxor RT, c, c; \
151 vpsrld $1, c, RT; \
153 vpor c, RT, c; \
158 vpaddd x, RK1, RT;\
160 vpxor RT, c, c; \
/Linux-v5.4/Documentation/locking/
Drt-mutex.rst2 RT-mutex subsystem with PI support
5 RT-mutexes with priority inheritance are used to support PI-futexes,
16 RT-mutexes extend the semantics of simple mutexes by the priority
40 RT-mutexes are optimized for fastpath operations and have no internal
/Linux-v5.4/arch/nds32/mm/
Dalignment.c18 #define RT(inst) (((inst) >> 20) & 0x1FUL) macro
488 *idx_to_addr(regs, RT(inst)) = in do_32()
491 *idx_to_addr(regs, RT(inst)) = target_val; in do_32()
497 target_val = *idx_to_addr(regs, RT(inst)); in do_32()
/Linux-v5.4/Documentation/block/
Dioprio.rst24 care, one io RT process can starve the entire system. Within the RT class,
/Linux-v5.4/arch/arm/mach-sa1100/
Dsleep.S119 @ Step 1 clear RT field of all MSCx registers
/Linux-v5.4/Documentation/
Dpi-futex.txt39 I.e. critical RT apps often choose lock structures to protect critical
67 [this is a quite common scenario for most non-trivial RT applications],
/Linux-v5.4/drivers/gpu/drm/radeon/
Dsumod.h79 # define RT(x) ((x) << 0) macro
/Linux-v5.4/arch/mips/kernel/
Dtraps.c497 #define RT 0x001f0000 macro
555 regs->regs[(opcode & RT) >> 16] = value; in simulate_ll()
578 reg = (opcode & RT) >> 16; in simulate_sc()
667 int rt = (opcode & RT) >> 16; in simulate_rdhwr_normal()
/Linux-v5.4/Documentation/trace/
Dhwlat_detector.rst13 originally written for use by the "RT" patch since the Real Time
/Linux-v5.4/Documentation/scheduler/
Dsched-nice-design.rst84 run audio (and other multimedia) apps under RT priorities such as
Dsched-rt-group.rst110 SCHED_OTHER (non-RT tasks). These defaults were chosen so that a run-away
Dsched-deadline.rst216 - Umax is the maximum reclaimable utilization (subjected to RT throttling
221 (subjected to RT throttling limits).
567 tasks with real-time group scheduling (a.k.a. RT-throttling - see
575 A main difference between deadline bandwidth management and RT-throttling
/Linux-v5.4/Documentation/admin-guide/
Dsysrq.rst34 256 = 0x100 - allow nicing of all RT tasks
115 ``n`` Used to make RT tasks nice-able
/Linux-v5.4/Documentation/driver-api/gpio/
Ddriver.rst332 threaded on -RT. As a result, spinlock_t or any sleepable APIs (like PM
337 this way it will become a threaded IRQ handler on -RT and a hard IRQ handler
338 on non-RT (for example, see [3]).
362 Realtime considerations: this kind of handlers will be forced threaded on -RT,
/Linux-v5.4/Documentation/x86/
Dearlyprintk.rst141 …sks(I) saK show-backtrace-all-active-cpus(L) show-memory-usage(M) nice-all-RT-tasks(N) powerOff sh…

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