Searched refs:RREG8 (Results 1 – 10 of 10) sorted by relevance
96 status = RREG8(MGAREG_Status + 2); in mga_wait_busy()306 tmp = RREG8(MGAREG_CRTC_DATA); in mga_g200wb_set_plls()313 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()318 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()323 tmp = RREG8(MGAREG_MEM_MISC_READ); in mga_g200wb_set_plls()328 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()336 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()351 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()359 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()365 tmp = RREG8(DAC_DATA); in mga_g200wb_set_plls()[all …]
40 return RREG8(DAC_DATA); in mga_i2c_read_gpio()48 tmp = (RREG8(DAC_DATA) & mask) | val; in mga_i2c_set_gpio()
38 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg)) macro48 RREG8(0x1fda); \
36 #define RREG8(reg) ioread8(((void __iomem *)cdev->rmmio) + (reg)) macro77 RREG8(VGA_DAC_MASK); \78 RREG8(VGA_DAC_MASK); \79 RREG8(VGA_DAC_MASK); \80 RREG8(VGA_DAC_MASK); \
77 return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2; in xgpu_ai_peek_ack()86 reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE); in xgpu_ai_poll_ack()
1060 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) macro
293 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) in radeon_wait_pll_lock()
3780 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()3833 tmp = RREG8(R_0003C2_GENMO_WT); in r100_vga_render_disable()
2508 #define RREG8(reg) readb((rdev->rmmio) + (reg)) macro
1149 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_legacy_get_lvds_info_from_regs()
