Searched refs:RREG32_UVD_CTX (Results 1 – 8 of 8) sorted by relevance
302 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); in uvd_v4_2_start()582 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()591 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
742 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()751 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
70 return RREG32_UVD_CTX(index); in amdgpu_cgs_read_ind_register()
1400 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()1409 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1078 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) macro
5457 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()5469 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
2538 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) macro
6223 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in cik_enable_uvd_mgcg()6232 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in cik_enable_uvd_mgcg()