Home
last modified time | relevance | path

Searched refs:RREG32_PCIE (Results 1 – 25 of 25) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dcik.c1405 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1446 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_pcie_gen3_enable()
1453 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); in cik_pcie_gen3_enable()
1478 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1482 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1510 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1533 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1538 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1561 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in cik_program_aspm()
1568 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in cik_program_aspm()
[all …]
Dnbio_v6_1.c150 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_update_medium_grain_clock_gating()
178 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_update_medium_grain_light_sleep()
199 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_get_clockgating_state()
204 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_get_clockgating_state()
265 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); in nbio_v6_1_init_registers()
272 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); in nbio_v6_1_init_registers()
Dnbio_v2_3.c192 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_update_medium_grain_clock_gating()
218 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_update_medium_grain_light_sleep()
239 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_get_clockgating_state()
244 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_get_clockgating_state()
305 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); in nbio_v2_3_init_registers()
Dnbio_v7_0.c163 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); in nbio_v7_0_update_medium_grain_clock_gating()
201 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_update_medium_grain_light_sleep()
222 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_0_get_clockgating_state()
227 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_get_clockgating_state()
Dnbio_v7_4.c202 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_update_medium_grain_light_sleep()
223 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_4_get_clockgating_state()
228 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_get_clockgating_state()
311 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); in nbio_v7_4_init_registers()
Dsi.c1376 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in si_get_pcie_usage()
1381 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in si_get_pcie_usage()
1382 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in si_get_pcie_usage()
1390 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in si_get_pcie_replay_count()
1391 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); in si_get_pcie_replay_count()
1694 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
1847 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
2010 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
2018 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
Dsoc15.c844 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); in soc15_get_pcie_usage()
849 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in soc15_get_pcie_usage()
850 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in soc15_get_pcie_usage()
893 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); in vega20_get_pcie_usage()
898 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); in vega20_get_pcie_usage()
899 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); in vega20_get_pcie_usage()
930 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); in soc15_get_pcie_replay_count()
931 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); in soc15_get_pcie_replay_count()
Dvi.c988 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in vi_get_pcie_usage()
993 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in vi_get_pcie_usage()
994 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in vi_get_pcie_usage()
1002 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in vi_get_pcie_replay_count()
1003 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); in vi_get_pcie_replay_count()
1362 temp = data = RREG32_PCIE(ixPCIE_CNTL2); in vi_update_bif_medium_grain_light_sleep()
1625 data = RREG32_PCIE(ixPCIE_CNTL2); in vi_common_get_clockgating_state()
Damdgpu_cgs.c66 return RREG32_PCIE(index); in amdgpu_cgs_read_ind_register()
Dpsp_v3_1.c598 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); in psp_v3_1_smu_reload_quirk()
Damdgpu_debugfs.c243 value = RREG32_PCIE(*pos >> 2); in amdgpu_debugfs_regs_pcie_read()
Damdgpu.h1070 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) macro
Dgmc_v7_0.c838 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in gmc_v7_0_enable_bif_mgls()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dr300.c95 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
97 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
181 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()
201 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()
539 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
555 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
557 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
573 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_get_pcie_lanes()
600 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info()
602 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); in rv370_debugfs_pcie_gart_info()
[all …]
Dsi.c5572 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()
7156 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
7271 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
7434 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
7442 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
Drv6xx_dpm.c130 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv6xx_enable_pll_sleep_in_l1()
Drv770_dpm.c121 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv770_enable_pll_sleep_in_l1()
Dradeon.h2524 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) macro
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/smumgr/
Dsmu9_smumgr.c43 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu9_is_smc_ram_running()
Dvega20_smumgr.c52 mp1_fw_flags = RREG32_PCIE(MP1_Public | in vega20_is_smc_ram_running()
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/
Dsmu_v12_0.c140 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v12_0_check_fw_status()
Dsmu_v11_0.c233 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_load_microcode()
252 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_check_fw_status()
Dnavi10_ppt.c309 mp0_fw_intf = RREG32_PCIE(MP0_Public | in is_asic_secure()
Dvega20_ppt.c1060 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in vega20_print_clk_levels()
1063 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_print_clk_levels()
/Linux-v5.4/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega20_hwmgr.c3355 current_gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in vega20_print_clock_levels()
3358 current_lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega20_print_clock_levels()