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Searched refs:RLC_PG_CNTL (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/radeon/
Dcik.c6372 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pu()
6378 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pu()
6386 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pd()
6392 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pd()
6399 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_cp_pg()
6405 WREG32(RLC_PG_CNTL, data); in cik_enable_cp_pg()
6412 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gds_pg()
6418 WREG32(RLC_PG_CNTL, data); in cik_enable_gds_pg()
6515 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_cgpg()
6518 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
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Dsid.h1326 #define RLC_PG_CNTL 0xC35C macro
Dcikd.h1425 #define RLC_PG_CNTL 0xC40C macro
Dsi.c5263 tmp = RREG32(RLC_PG_CNTL); in si_enable_gfx_cgpg()
5265 WREG32(RLC_PG_CNTL, tmp); in si_enable_gfx_cgpg()
5285 tmp = RREG32(RLC_PG_CNTL); in si_init_gfx_cgpg()
5287 WREG32(RLC_PG_CNTL, tmp); in si_init_gfx_cgpg()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v8_0.c4067 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_up()
4073 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_down()
4078 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); in cz_enable_cp_power_gating()
5368 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_static_mg_power_gating()
5374 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_dynamic_mg_power_gating()
5380 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0); in polaris11_enable_gfx_quick_mg_power_gating()
5386 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0); in cz_enable_gfx_cg_power_gating()
5392 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0); in cz_enable_gfx_pipeline_power_gating()
Dgfx_v9_0.c2833 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_sck_slow_down_on_power_up()
2847 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_sck_slow_down_on_power_down()
2861 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_cp_power_gating()
2874 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_cg_power_gating()
2887 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_pipeline_powergating()
2904 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_static_mg_power_gating()
2917 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_dynamic_mg_power_gating()
Dsid.h1355 #define RLC_PG_CNTL 0x30D7 macro
Dgfx_v6_0.c2776 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); in gfx_v6_0_enable_gfx_cgpg()
2829 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); in gfx_v6_0_init_gfx_cgpg()