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Searched refs:RG_PE1_H_PLL_REG (Results 1 – 1 of 1) sorted by relevance

/Linux-v5.4/drivers/staging/mt7621-pci-phy/
Dpci-mt7621-phy.c37 #define RG_PE1_H_PLL_REG 0x490 macro
162 val = phy_read(phy, RG_PE1_H_PLL_REG); in mt7621_set_phy_for_ssc()
167 phy_write(phy, val, RG_PE1_H_PLL_REG); in mt7621_set_phy_for_ssc()
171 phy_write(phy, val, RG_PE1_H_PLL_REG); in mt7621_set_phy_for_ssc()
212 val = phy_read(phy, RG_PE1_H_PLL_REG); in mt7621_set_phy_for_ssc()
220 phy_write(phy, val, RG_PE1_H_PLL_REG); in mt7621_set_phy_for_ssc()