1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 /***************************************************************************** 8 * 9 * Module: __INC_HAL8192CPHYREG_H 10 * 11 * 12 * Note: 1. Define PMAC/BB register map 13 * 2. Define RF register map 14 * 3. PMAC/BB register bit mask. 15 * 4. RF reg bit mask. 16 * 5. Other BB/RF relative definition. 17 * 18 * 19 * Export: Constants, macro, functions(API), global variables(None). 20 * 21 * Abbrev: 22 * 23 * History: 24 * Data Who Remark 25 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 26 * 2. Reorganize code architecture. 27 *09/25/2008 MH 1. Add RL6052 register definition 28 * 29 *****************************************************************************/ 30 #ifndef __INC_HAL8192CPHYREG_H 31 #define __INC_HAL8192CPHYREG_H 32 33 34 /*--------------------------Define Parameters-------------------------------*/ 35 36 /* */ 37 /* 8192S Regsiter offset definition */ 38 /* */ 39 40 /* */ 41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 42 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 43 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 44 /* 3. RF register 0x00-2E */ 45 /* 4. Bit Mask for BB/RF register */ 46 /* 5. Other defintion for BB/RF R/W */ 47 /* */ 48 49 50 /* */ 51 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 52 /* 1. Page1(0x100) */ 53 /* */ 54 #define rPMAC_Reset 0x100 55 #define rPMAC_TxStart 0x104 56 #define rPMAC_TxLegacySIG 0x108 57 #define rPMAC_TxHTSIG1 0x10c 58 #define rPMAC_TxHTSIG2 0x110 59 #define rPMAC_PHYDebug 0x114 60 #define rPMAC_TxPacketNum 0x118 61 #define rPMAC_TxIdle 0x11c 62 #define rPMAC_TxMACHeader0 0x120 63 #define rPMAC_TxMACHeader1 0x124 64 #define rPMAC_TxMACHeader2 0x128 65 #define rPMAC_TxMACHeader3 0x12c 66 #define rPMAC_TxMACHeader4 0x130 67 #define rPMAC_TxMACHeader5 0x134 68 #define rPMAC_TxDataType 0x138 69 #define rPMAC_TxRandomSeed 0x13c 70 #define rPMAC_CCKPLCPPreamble 0x140 71 #define rPMAC_CCKPLCPHeader 0x144 72 #define rPMAC_CCKCRC16 0x148 73 #define rPMAC_OFDMRxCRC32OK 0x170 74 #define rPMAC_OFDMRxCRC32Er 0x174 75 #define rPMAC_OFDMRxParityEr 0x178 76 #define rPMAC_OFDMRxCRC8Er 0x17c 77 #define rPMAC_CCKCRxRC16Er 0x180 78 #define rPMAC_CCKCRxRC32Er 0x184 79 #define rPMAC_CCKCRxRC32OK 0x188 80 #define rPMAC_TxStatus 0x18c 81 82 /* */ 83 /* 2. Page2(0x200) */ 84 /* */ 85 /* The following two definition are only used for USB interface. */ 86 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 87 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 88 89 /* */ 90 /* 3. Page8(0x800) */ 91 /* */ 92 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ 93 94 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 95 #define rFPGA0_PSDFunction 0x808 96 97 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 98 99 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 100 #define rFPGA0_RFTiming2 0x814 101 102 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 103 #define rFPGA0_XA_HSSIParameter2 0x824 104 #define rFPGA0_XB_HSSIParameter1 0x828 105 #define rFPGA0_XB_HSSIParameter2 0x82c 106 #define rTxAGC_B_Rate18_06 0x830 107 #define rTxAGC_B_Rate54_24 0x834 108 #define rTxAGC_B_CCK1_55_Mcs32 0x838 109 #define rTxAGC_B_Mcs03_Mcs00 0x83c 110 111 #define rTxAGC_B_Mcs07_Mcs04 0x848 112 #define rTxAGC_B_Mcs11_Mcs08 0x84c 113 114 #define rFPGA0_XA_LSSIParameter 0x840 115 #define rFPGA0_XB_LSSIParameter 0x844 116 117 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 118 #define rFPGA0_RFSleepUpParameter 0x854 119 120 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 121 #define rFPGA0_XCD_SwitchControl 0x85c 122 123 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 124 #define rFPGA0_XB_RFInterfaceOE 0x864 125 126 #define rTxAGC_B_Mcs15_Mcs12 0x868 127 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 128 129 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 130 #define rFPGA0_XCD_RFInterfaceSW 0x874 131 132 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 133 #define rFPGA0_XCD_RFParameter 0x87c 134 135 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 136 #define rFPGA0_AnalogParameter2 0x884 137 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 138 #define rFPGA0_AnalogParameter4 0x88c 139 140 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 141 #define rFPGA0_XB_LSSIReadBack 0x8a4 142 #define rFPGA0_XC_LSSIReadBack 0x8a8 143 #define rFPGA0_XD_LSSIReadBack 0x8ac 144 145 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 146 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 147 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 148 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */ 149 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 150 151 /* */ 152 /* 4. Page9(0x900) */ 153 /* */ 154 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */ 155 156 #define rFPGA1_TxBlock 0x904 /* Useless now */ 157 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 158 #define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */ 159 #define rS0S1_PathSwitch 0x948 160 161 /* */ 162 /* 5. PageA(0xA00) */ 163 /* */ 164 /* Set Control channel to upper or lower. These settings are required only for 40MHz */ 165 #define rCCK0_System 0xa00 166 167 #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */ 168 #define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */ 169 170 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 171 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 172 173 #define rCCK0_RxHP 0xa14 174 175 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 176 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 177 178 #define rCCK0_TxFilter1 0xa20 179 #define rCCK0_TxFilter2 0xa24 180 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 181 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 182 #define rCCK0_TRSSIReport 0xa50 183 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 184 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 185 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 186 /* */ 187 /* PageB(0xB00) */ 188 /* */ 189 #define rPdp_AntA 0xb00 190 #define rPdp_AntA_4 0xb04 191 #define rConfig_Pmpd_AntA 0xb28 192 #define rConfig_AntA 0xb68 193 #define rConfig_AntB 0xb6c 194 #define rPdp_AntB 0xb70 195 #define rPdp_AntB_4 0xb74 196 #define rConfig_Pmpd_AntB 0xb98 197 #define rAPK 0xbd8 198 199 /* */ 200 /* 6. PageC(0xC00) */ 201 /* */ 202 #define rOFDM0_LSTF 0xc00 203 204 #define rOFDM0_TRxPathEnable 0xc04 205 #define rOFDM0_TRMuxPar 0xc08 206 #define rOFDM0_TRSWIsolation 0xc0c 207 208 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 209 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 210 #define rOFDM0_XBRxAFE 0xc18 211 #define rOFDM0_XBRxIQImbalance 0xc1c 212 #define rOFDM0_XCRxAFE 0xc20 213 #define rOFDM0_XCRxIQImbalance 0xc24 214 #define rOFDM0_XDRxAFE 0xc28 215 #define rOFDM0_XDRxIQImbalance 0xc2c 216 217 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD DM tune init gain */ 218 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 219 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 220 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 221 222 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 223 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 224 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 225 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 226 227 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 228 #define rOFDM0_XAAGCCore2 0xc54 229 #define rOFDM0_XBAGCCore1 0xc58 230 #define rOFDM0_XBAGCCore2 0xc5c 231 #define rOFDM0_XCAGCCore1 0xc60 232 #define rOFDM0_XCAGCCore2 0xc64 233 #define rOFDM0_XDAGCCore1 0xc68 234 #define rOFDM0_XDAGCCore2 0xc6c 235 236 #define rOFDM0_AGCParameter1 0xc70 237 #define rOFDM0_AGCParameter2 0xc74 238 #define rOFDM0_AGCRSSITable 0xc78 239 #define rOFDM0_HTSTFAGC 0xc7c 240 241 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 242 #define rOFDM0_XATxAFE 0xc84 243 #define rOFDM0_XBTxIQImbalance 0xc88 244 #define rOFDM0_XBTxAFE 0xc8c 245 #define rOFDM0_XCTxIQImbalance 0xc90 246 #define rOFDM0_XCTxAFE 0xc94 247 #define rOFDM0_XDTxIQImbalance 0xc98 248 #define rOFDM0_XDTxAFE 0xc9c 249 250 #define rOFDM0_RxIQExtAnta 0xca0 251 #define rOFDM0_TxCoeff1 0xca4 252 #define rOFDM0_TxCoeff2 0xca8 253 #define rOFDM0_TxCoeff3 0xcac 254 #define rOFDM0_TxCoeff4 0xcb0 255 #define rOFDM0_TxCoeff5 0xcb4 256 #define rOFDM0_TxCoeff6 0xcb8 257 #define rOFDM0_RxHPParameter 0xce0 258 #define rOFDM0_TxPseudoNoiseWgt 0xce4 259 #define rOFDM0_FrameSync 0xcf0 260 #define rOFDM0_DFSReport 0xcf4 261 262 /* */ 263 /* 7. PageD(0xD00) */ 264 /* */ 265 #define rOFDM1_LSTF 0xd00 266 #define rOFDM1_TRxPathEnable 0xd04 267 268 #define rOFDM1_CFO 0xd08 /* No setting now */ 269 #define rOFDM1_CSI1 0xd10 270 #define rOFDM1_SBD 0xd14 271 #define rOFDM1_CSI2 0xd18 272 #define rOFDM1_CFOTracking 0xd2c 273 #define rOFDM1_TRxMesaure1 0xd34 274 #define rOFDM1_IntfDet 0xd3c 275 #define rOFDM1_PseudoNoiseStateAB 0xd50 276 #define rOFDM1_PseudoNoiseStateCD 0xd54 277 #define rOFDM1_RxPseudoNoiseWgt 0xd58 278 279 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 280 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 281 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 282 283 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 284 #define rOFDM_ShortCFOCD 0xdb0 285 #define rOFDM_LongCFOAB 0xdb4 286 #define rOFDM_LongCFOCD 0xdb8 287 #define rOFDM_TailCFOAB 0xdbc 288 #define rOFDM_TailCFOCD 0xdc0 289 #define rOFDM_PWMeasure1 0xdc4 290 #define rOFDM_PWMeasure2 0xdc8 291 #define rOFDM_BWReport 0xdcc 292 #define rOFDM_AGCReport 0xdd0 293 #define rOFDM_RxSNR 0xdd4 294 #define rOFDM_RxEVMCSI 0xdd8 295 #define rOFDM_SIGReport 0xddc 296 297 298 /* */ 299 /* 8. PageE(0xE00) */ 300 /* */ 301 #define rTxAGC_A_Rate18_06 0xe00 302 #define rTxAGC_A_Rate54_24 0xe04 303 #define rTxAGC_A_CCK1_Mcs32 0xe08 304 #define rTxAGC_A_Mcs03_Mcs00 0xe10 305 #define rTxAGC_A_Mcs07_Mcs04 0xe14 306 #define rTxAGC_A_Mcs11_Mcs08 0xe18 307 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 308 309 #define rFPGA0_IQK 0xe28 310 #define rTx_IQK_Tone_A 0xe30 311 #define rRx_IQK_Tone_A 0xe34 312 #define rTx_IQK_PI_A 0xe38 313 #define rRx_IQK_PI_A 0xe3c 314 315 #define rTx_IQK 0xe40 316 #define rRx_IQK 0xe44 317 #define rIQK_AGC_Pts 0xe48 318 #define rIQK_AGC_Rsp 0xe4c 319 #define rTx_IQK_Tone_B 0xe50 320 #define rRx_IQK_Tone_B 0xe54 321 #define rTx_IQK_PI_B 0xe58 322 #define rRx_IQK_PI_B 0xe5c 323 #define rIQK_AGC_Cont 0xe60 324 325 #define rBlue_Tooth 0xe6c 326 #define rRx_Wait_CCA 0xe70 327 #define rTx_CCK_RFON 0xe74 328 #define rTx_CCK_BBON 0xe78 329 #define rTx_OFDM_RFON 0xe7c 330 #define rTx_OFDM_BBON 0xe80 331 #define rTx_To_Rx 0xe84 332 #define rTx_To_Tx 0xe88 333 #define rRx_CCK 0xe8c 334 335 #define rTx_Power_Before_IQK_A 0xe94 336 #define rTx_Power_After_IQK_A 0xe9c 337 338 #define rRx_Power_Before_IQK_A 0xea0 339 #define rRx_Power_Before_IQK_A_2 0xea4 340 #define rRx_Power_After_IQK_A 0xea8 341 #define rRx_Power_After_IQK_A_2 0xeac 342 343 #define rTx_Power_Before_IQK_B 0xeb4 344 #define rTx_Power_After_IQK_B 0xebc 345 346 #define rRx_Power_Before_IQK_B 0xec0 347 #define rRx_Power_Before_IQK_B_2 0xec4 348 #define rRx_Power_After_IQK_B 0xec8 349 #define rRx_Power_After_IQK_B_2 0xecc 350 351 #define rRx_OFDM 0xed0 352 #define rRx_Wait_RIFS 0xed4 353 #define rRx_TO_Rx 0xed8 354 #define rStandby 0xedc 355 #define rSleep 0xee0 356 #define rPMPD_ANAEN 0xeec 357 358 /* */ 359 /* 7. RF Register 0x00-0x2E (RF 8256) */ 360 /* RF-0222D 0x00-3F */ 361 /* */ 362 /* Zebra1 */ 363 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 364 #define rZebra1_TRxEnable1 0x1 365 #define rZebra1_TRxEnable2 0x2 366 #define rZebra1_AGC 0x4 367 #define rZebra1_ChargePump 0x5 368 #define rZebra1_Channel 0x7 /* RF channel switch */ 369 370 /* endif */ 371 #define rZebra1_TxGain 0x8 /* Useless now */ 372 #define rZebra1_TxLPF 0x9 373 #define rZebra1_RxLPF 0xb 374 #define rZebra1_RxHPFCorner 0xc 375 376 /* Zebra4 */ 377 #define rGlobalCtrl 0 /* Useless now */ 378 #define rRTL8256_TxLPF 19 379 #define rRTL8256_RxLPF 11 380 381 /* RTL8258 */ 382 #define rRTL8258_TxLPF 0x11 /* Useless now */ 383 #define rRTL8258_RxLPF 0x13 384 #define rRTL8258_RSSILPF 0xa 385 386 /* */ 387 /* RL6052 Register definition */ 388 /* */ 389 #define RF_AC 0x00 /* */ 390 391 #define RF_IQADJ_G1 0x01 /* */ 392 #define RF_IQADJ_G2 0x02 /* */ 393 #define RF_BS_PA_APSET_G1_G4 0x03 394 #define RF_BS_PA_APSET_G5_G8 0x04 395 #define RF_POW_TRSW 0x05 /* */ 396 397 #define RF_GAIN_RX 0x06 /* */ 398 #define RF_GAIN_TX 0x07 /* */ 399 400 #define RF_TXM_IDAC 0x08 /* */ 401 #define RF_IPA_G 0x09 /* */ 402 #define RF_TXBIAS_G 0x0A 403 #define RF_TXPA_AG 0x0B 404 #define RF_IPA_A 0x0C /* */ 405 #define RF_TXBIAS_A 0x0D 406 #define RF_BS_PA_APSET_G9_G11 0x0E 407 #define RF_BS_IQGEN 0x0F /* */ 408 409 #define RF_MODE1 0x10 /* */ 410 #define RF_MODE2 0x11 /* */ 411 412 #define RF_RX_AGC_HP 0x12 /* */ 413 #define RF_TX_AGC 0x13 /* */ 414 #define RF_BIAS 0x14 /* */ 415 #define RF_IPA 0x15 /* */ 416 #define RF_TXBIAS 0x16 /* */ 417 #define RF_POW_ABILITY 0x17 /* */ 418 #define RF_MODE_AG 0x18 /* */ 419 #define rRfChannel 0x18 /* RF channel and BW switch */ 420 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 421 #define RF_TOP 0x19 /* */ 422 423 #define RF_RX_G1 0x1A /* */ 424 #define RF_RX_G2 0x1B /* */ 425 426 #define RF_RX_BB2 0x1C /* */ 427 #define RF_RX_BB1 0x1D /* */ 428 429 #define RF_RCK1 0x1E /* */ 430 #define RF_RCK2 0x1F /* */ 431 432 #define RF_TX_G1 0x20 /* */ 433 #define RF_TX_G2 0x21 /* */ 434 #define RF_TX_G3 0x22 /* */ 435 436 #define RF_TX_BB1 0x23 /* */ 437 438 #define RF_T_METER 0x24 /* */ 439 440 #define RF_SYN_G1 0x25 /* RF TX Power control */ 441 #define RF_SYN_G2 0x26 /* RF TX Power control */ 442 #define RF_SYN_G3 0x27 /* RF TX Power control */ 443 #define RF_SYN_G4 0x28 /* RF TX Power control */ 444 #define RF_SYN_G5 0x29 /* RF TX Power control */ 445 #define RF_SYN_G6 0x2A /* RF TX Power control */ 446 #define RF_SYN_G7 0x2B /* RF TX Power control */ 447 #define RF_SYN_G8 0x2C /* RF TX Power control */ 448 449 #define RF_RCK_OS 0x30 /* RF TX PA control */ 450 451 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 452 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 453 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 454 #define RF_TX_BIAS_A 0x35 455 #define RF_TX_BIAS_D 0x36 456 #define RF_LOBF_9 0x38 457 #define RF_RXRF_A3 0x3C /* */ 458 #define RF_TRSW 0x3F 459 460 #define RF_TXRF_A2 0x41 461 #define RF_TXPA_G4 0x46 462 #define RF_TXPA_A4 0x4B 463 #define RF_0x52 0x52 464 #define RF_WE_LUT 0xEF 465 #define RF_S0S1 0xB0 466 467 /* */ 468 /* Bit Mask */ 469 /* */ 470 /* 1. Page1(0x100) */ 471 #define bBBResetB 0x100 /* Useless now? */ 472 #define bGlobalResetB 0x200 473 #define bOFDMTxStart 0x4 474 #define bCCKTxStart 0x8 475 #define bCRC32Debug 0x100 476 #define bPMACLoopback 0x10 477 #define bTxLSIG 0xffffff 478 #define bOFDMTxRate 0xf 479 #define bOFDMTxReserved 0x10 480 #define bOFDMTxLength 0x1ffe0 481 #define bOFDMTxParity 0x20000 482 #define bTxHTSIG1 0xffffff 483 #define bTxHTMCSRate 0x7f 484 #define bTxHTBW 0x80 485 #define bTxHTLength 0xffff00 486 #define bTxHTSIG2 0xffffff 487 #define bTxHTSmoothing 0x1 488 #define bTxHTSounding 0x2 489 #define bTxHTReserved 0x4 490 #define bTxHTAggreation 0x8 491 #define bTxHTSTBC 0x30 492 #define bTxHTAdvanceCoding 0x40 493 #define bTxHTShortGI 0x80 494 #define bTxHTNumberHT_LTF 0x300 495 #define bTxHTCRC8 0x3fc00 496 #define bCounterReset 0x10000 497 #define bNumOfOFDMTx 0xffff 498 #define bNumOfCCKTx 0xffff0000 499 #define bTxIdleInterval 0xffff 500 #define bOFDMService 0xffff0000 501 #define bTxMACHeader 0xffffffff 502 #define bTxDataInit 0xff 503 #define bTxHTMode 0x100 504 #define bTxDataType 0x30000 505 #define bTxRandomSeed 0xffffffff 506 #define bCCKTxPreamble 0x1 507 #define bCCKTxSFD 0xffff0000 508 #define bCCKTxSIG 0xff 509 #define bCCKTxService 0xff00 510 #define bCCKLengthExt 0x8000 511 #define bCCKTxLength 0xffff0000 512 #define bCCKTxCRC16 0xffff 513 #define bCCKTxStatus 0x1 514 #define bOFDMTxStatus 0x2 515 516 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 517 518 /* 2. Page8(0x800) */ 519 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 520 #define bJapanMode 0x2 521 #define bCCKTxSC 0x30 522 #define bCCKEn 0x1000000 523 #define bOFDMEn 0x2000000 524 525 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 526 #define bOFDMTxDACPhase 0x40000 527 #define bXATxAGC 0x3f 528 529 #define bAntennaSelect 0x0300 530 531 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 532 #define bXCTxAGC 0xf000 533 #define bXDTxAGC 0xf0000 534 535 #define bPAStart 0xf0000000 /* Useless now */ 536 #define bTRStart 0x00f00000 537 #define bRFStart 0x0000f000 538 #define bBBStart 0x000000f0 539 #define bBBCCKStart 0x0000000f 540 #define bPAEnd 0xf /* Reg0x814 */ 541 #define bTREnd 0x0f000000 542 #define bRFEnd 0x000f0000 543 #define bCCAMask 0x000000f0 /* T2R */ 544 #define bR2RCCAMask 0x00000f00 545 #define bHSSI_R2TDelay 0xf8000000 546 #define bHSSI_T2RDelay 0xf80000 547 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 548 #define bIGFromCCK 0x200 549 #define bAGCAddress 0x3f 550 #define bRxHPTx 0x7000 551 #define bRxHPT2R 0x38000 552 #define bRxHPCCKIni 0xc0000 553 #define bAGCTxCode 0xc00000 554 #define bAGCRxCode 0x300000 555 556 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 557 #define b3WireAddressLength 0x400 558 559 #define b3WireRFPowerDown 0x1 /* Useless now */ 560 /* define bHWSISelect 0x8 */ 561 #define b5GPAPEPolarity 0x40000000 562 #define b2GPAPEPolarity 0x80000000 563 #define bRFSW_TxDefaultAnt 0x3 564 #define bRFSW_TxOptionAnt 0x30 565 #define bRFSW_RxDefaultAnt 0x300 566 #define bRFSW_RxOptionAnt 0x3000 567 #define bRFSI_3WireData 0x1 568 #define bRFSI_3WireClock 0x2 569 #define bRFSI_3WireLoad 0x4 570 #define bRFSI_3WireRW 0x8 571 #define bRFSI_3Wire 0xf 572 573 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 574 575 #define bRFSI_TRSW 0x20 /* Useless now */ 576 #define bRFSI_TRSWB 0x40 577 #define bRFSI_ANTSW 0x100 578 #define bRFSI_ANTSWB 0x200 579 #define bRFSI_PAPE 0x400 580 #define bRFSI_PAPE5G 0x800 581 #define bBandSelect 0x1 582 #define bHTSIG2_GI 0x80 583 #define bHTSIG2_Smoothing 0x01 584 #define bHTSIG2_Sounding 0x02 585 #define bHTSIG2_Aggreaton 0x08 586 #define bHTSIG2_STBC 0x30 587 #define bHTSIG2_AdvCoding 0x40 588 #define bHTSIG2_NumOfHTLTF 0x300 589 #define bHTSIG2_CRC8 0x3fc 590 #define bHTSIG1_MCS 0x7f 591 #define bHTSIG1_BandWidth 0x80 592 #define bHTSIG1_HTLength 0xffff 593 #define bLSIG_Rate 0xf 594 #define bLSIG_Reserved 0x10 595 #define bLSIG_Length 0x1fffe 596 #define bLSIG_Parity 0x20 597 #define bCCKRxPhase 0x4 598 599 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 600 601 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 602 603 #define bLSSIReadBackData 0xfffff /* T65 RF */ 604 605 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 606 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 607 #define bRegulator0Standby 0x1 608 #define bRegulatorPLLStandby 0x2 609 #define bRegulator1Standby 0x4 610 #define bPLLPowerUp 0x8 611 #define bDPLLPowerUp 0x10 612 #define bDA10PowerUp 0x20 613 #define bAD7PowerUp 0x200 614 #define bDA6PowerUp 0x2000 615 #define bXtalPowerUp 0x4000 616 #define b40MDClkPowerUP 0x8000 617 #define bDA6DebugMode 0x20000 618 #define bDA6Swing 0x380000 619 620 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 621 622 #define b80MClkDelay 0x18000000 /* Useless */ 623 #define bAFEWatchDogEnable 0x20000000 624 625 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 626 #define bXtalCap23 0x3 627 #define bXtalCap92x 0x0f000000 628 #define bXtalCap 0x0f000000 629 630 #define bIntDifClkEnable 0x400 /* Useless */ 631 #define bExtSigClkEnable 0x800 632 #define bBandgapMbiasPowerUp 0x10000 633 #define bAD11SHGain 0xc0000 634 #define bAD11InputRange 0x700000 635 #define bAD11OPCurrent 0x3800000 636 #define bIPathLoopback 0x4000000 637 #define bQPathLoopback 0x8000000 638 #define bAFELoopback 0x10000000 639 #define bDA10Swing 0x7e0 640 #define bDA10Reverse 0x800 641 #define bDAClkSource 0x1000 642 #define bAD7InputRange 0x6000 643 #define bAD7Gain 0x38000 644 #define bAD7OutputCMMode 0x40000 645 #define bAD7InputCMMode 0x380000 646 #define bAD7Current 0xc00000 647 #define bRegulatorAdjust 0x7000000 648 #define bAD11PowerUpAtTx 0x1 649 #define bDA10PSAtTx 0x10 650 #define bAD11PowerUpAtRx 0x100 651 #define bDA10PSAtRx 0x1000 652 #define bCCKRxAGCFormat 0x200 653 #define bPSDFFTSamplepPoint 0xc000 654 #define bPSDAverageNum 0x3000 655 #define bIQPathControl 0xc00 656 #define bPSDFreq 0x3ff 657 #define bPSDAntennaPath 0x30 658 #define bPSDIQSwitch 0x40 659 #define bPSDRxTrigger 0x400000 660 #define bPSDTxTrigger 0x80000000 661 #define bPSDSineToneScale 0x7f000000 662 #define bPSDReport 0xffff 663 664 /* 3. Page9(0x900) */ 665 #define bOFDMTxSC 0x30000000 /* Useless */ 666 #define bCCKTxOn 0x1 667 #define bOFDMTxOn 0x2 668 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 669 #define bDebugItem 0xff /* reset debug page and LWord */ 670 #define bAntL 0x10 671 #define bAntNonHT 0x100 672 #define bAntHT1 0x1000 673 #define bAntHT2 0x10000 674 #define bAntHT1S1 0x100000 675 #define bAntNonHTS1 0x1000000 676 677 /* 4. PageA(0xA00) */ 678 #define bCCKBBMode 0x3 /* Useless */ 679 #define bCCKTxPowerSaving 0x80 680 #define bCCKRxPowerSaving 0x40 681 682 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 683 684 #define bCCKScramble 0x8 /* Useless */ 685 #define bCCKAntDiversity 0x8000 686 #define bCCKCarrierRecovery 0x4000 687 #define bCCKTxRate 0x3000 688 #define bCCKDCCancel 0x0800 689 #define bCCKISICancel 0x0400 690 #define bCCKMatchFilter 0x0200 691 #define bCCKEqualizer 0x0100 692 #define bCCKPreambleDetect 0x800000 693 #define bCCKFastFalseCCA 0x400000 694 #define bCCKChEstStart 0x300000 695 #define bCCKCCACount 0x080000 696 #define bCCKcs_lim 0x070000 697 #define bCCKBistMode 0x80000000 698 #define bCCKCCAMask 0x40000000 699 #define bCCKTxDACPhase 0x4 700 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 701 #define bCCKr_cp_mode0 0x0100 702 #define bCCKTxDCOffset 0xf0 703 #define bCCKRxDCOffset 0xf 704 #define bCCKCCAMode 0xc000 705 #define bCCKFalseCS_lim 0x3f00 706 #define bCCKCS_ratio 0xc00000 707 #define bCCKCorgBit_sel 0x300000 708 #define bCCKPD_lim 0x0f0000 709 #define bCCKNewCCA 0x80000000 710 #define bCCKRxHPofIG 0x8000 711 #define bCCKRxIG 0x7f00 712 #define bCCKLNAPolarity 0x800000 713 #define bCCKRx1stGain 0x7f0000 714 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 715 #define bCCKRxAGCSatLevel 0x1f000000 716 #define bCCKRxAGCSatCount 0xe0 717 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 718 #define bCCKFixedRxAGC 0x8000 719 #define bCCKAntennaPolarity 0x2000 720 #define bCCKTxFilterType 0x0c00 721 #define bCCKRxAGCReportType 0x0300 722 #define bCCKRxDAGCEn 0x80000000 723 #define bCCKRxDAGCPeriod 0x20000000 724 #define bCCKRxDAGCSatLevel 0x1f000000 725 #define bCCKTimingRecovery 0x800000 726 #define bCCKTxC0 0x3f0000 727 #define bCCKTxC1 0x3f000000 728 #define bCCKTxC2 0x3f 729 #define bCCKTxC3 0x3f00 730 #define bCCKTxC4 0x3f0000 731 #define bCCKTxC5 0x3f000000 732 #define bCCKTxC6 0x3f 733 #define bCCKTxC7 0x3f00 734 #define bCCKDebugPort 0xff0000 735 #define bCCKDACDebug 0x0f000000 736 #define bCCKFalseAlarmEnable 0x8000 737 #define bCCKFalseAlarmRead 0x4000 738 #define bCCKTRSSI 0x7f 739 #define bCCKRxAGCReport 0xfe 740 #define bCCKRxReport_AntSel 0x80000000 741 #define bCCKRxReport_MFOff 0x40000000 742 #define bCCKRxRxReport_SQLoss 0x20000000 743 #define bCCKRxReport_Pktloss 0x10000000 744 #define bCCKRxReport_Lockedbit 0x08000000 745 #define bCCKRxReport_RateError 0x04000000 746 #define bCCKRxReport_RxRate 0x03000000 747 #define bCCKRxFACounterLower 0xff 748 #define bCCKRxFACounterUpper 0xff000000 749 #define bCCKRxHPAGCStart 0xe000 750 #define bCCKRxHPAGCFinal 0x1c00 751 #define bCCKRxFalseAlarmEnable 0x8000 752 #define bCCKFACounterFreeze 0x4000 753 #define bCCKTxPathSel 0x10000000 754 #define bCCKDefaultRxPath 0xc000000 755 #define bCCKOptionRxPath 0x3000000 756 757 /* 5. PageC(0xC00) */ 758 #define bNumOfSTF 0x3 /* Useless */ 759 #define bShift_L 0xc0 760 #define bGI_TH 0xc 761 #define bRxPathA 0x1 762 #define bRxPathB 0x2 763 #define bRxPathC 0x4 764 #define bRxPathD 0x8 765 #define bTxPathA 0x1 766 #define bTxPathB 0x2 767 #define bTxPathC 0x4 768 #define bTxPathD 0x8 769 #define bTRSSIFreq 0x200 770 #define bADCBackoff 0x3000 771 #define bDFIRBackoff 0xc000 772 #define bTRSSILatchPhase 0x10000 773 #define bRxIDCOffset 0xff 774 #define bRxQDCOffset 0xff00 775 #define bRxDFIRMode 0x1800000 776 #define bRxDCNFType 0xe000000 777 #define bRXIQImb_A 0x3ff 778 #define bRXIQImb_B 0xfc00 779 #define bRXIQImb_C 0x3f0000 780 #define bRXIQImb_D 0xffc00000 781 #define bDC_dc_Notch 0x60000 782 #define bRxNBINotch 0x1f000000 783 #define bPD_TH 0xf 784 #define bPD_TH_Opt2 0xc000 785 #define bPWED_TH 0x700 786 #define bIfMF_Win_L 0x800 787 #define bPD_Option 0x1000 788 #define bMF_Win_L 0xe000 789 #define bBW_Search_L 0x30000 790 #define bwin_enh_L 0xc0000 791 #define bBW_TH 0x700000 792 #define bED_TH2 0x3800000 793 #define bBW_option 0x4000000 794 #define bRatio_TH 0x18000000 795 #define bWindow_L 0xe0000000 796 #define bSBD_Option 0x1 797 #define bFrame_TH 0x1c 798 #define bFS_Option 0x60 799 #define bDC_Slope_check 0x80 800 #define bFGuard_Counter_DC_L 0xe00 801 #define bFrame_Weight_Short 0x7000 802 #define bSub_Tune 0xe00000 803 #define bFrame_DC_Length 0xe000000 804 #define bSBD_start_offset 0x30000000 805 #define bFrame_TH_2 0x7 806 #define bFrame_GI2_TH 0x38 807 #define bGI2_Sync_en 0x40 808 #define bSarch_Short_Early 0x300 809 #define bSarch_Short_Late 0xc00 810 #define bSarch_GI2_Late 0x70000 811 #define bCFOAntSum 0x1 812 #define bCFOAcc 0x2 813 #define bCFOStartOffset 0xc 814 #define bCFOLookBack 0x70 815 #define bCFOSumWeight 0x80 816 #define bDAGCEnable 0x10000 817 #define bTXIQImb_A 0x3ff 818 #define bTXIQImb_B 0xfc00 819 #define bTXIQImb_C 0x3f0000 820 #define bTXIQImb_D 0xffc00000 821 #define bTxIDCOffset 0xff 822 #define bTxQDCOffset 0xff00 823 #define bTxDFIRMode 0x10000 824 #define bTxPesudoNoiseOn 0x4000000 825 #define bTxPesudoNoise_A 0xff 826 #define bTxPesudoNoise_B 0xff00 827 #define bTxPesudoNoise_C 0xff0000 828 #define bTxPesudoNoise_D 0xff000000 829 #define bCCADropOption 0x20000 830 #define bCCADropThres 0xfff00000 831 #define bEDCCA_H 0xf 832 #define bEDCCA_L 0xf0 833 #define bLambda_ED 0x300 834 #define bRxInitialGain 0x7f 835 #define bRxAntDivEn 0x80 836 #define bRxAGCAddressForLNA 0x7f00 837 #define bRxHighPowerFlow 0x8000 838 #define bRxAGCFreezeThres 0xc0000 839 #define bRxFreezeStep_AGC1 0x300000 840 #define bRxFreezeStep_AGC2 0xc00000 841 #define bRxFreezeStep_AGC3 0x3000000 842 #define bRxFreezeStep_AGC0 0xc000000 843 #define bRxRssi_Cmp_En 0x10000000 844 #define bRxQuickAGCEn 0x20000000 845 #define bRxAGCFreezeThresMode 0x40000000 846 #define bRxOverFlowCheckType 0x80000000 847 #define bRxAGCShift 0x7f 848 #define bTRSW_Tri_Only 0x80 849 #define bPowerThres 0x300 850 #define bRxAGCEn 0x1 851 #define bRxAGCTogetherEn 0x2 852 #define bRxAGCMin 0x4 853 #define bRxHP_Ini 0x7 854 #define bRxHP_TRLNA 0x70 855 #define bRxHP_RSSI 0x700 856 #define bRxHP_BBP1 0x7000 857 #define bRxHP_BBP2 0x70000 858 #define bRxHP_BBP3 0x700000 859 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 860 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 861 #define bRxSettle_TRSW 0x7 862 #define bRxSettle_LNA 0x38 863 #define bRxSettle_RSSI 0x1c0 864 #define bRxSettle_BBP 0xe00 865 #define bRxSettle_RxHP 0x7000 866 #define bRxSettle_AntSW_RSSI 0x38000 867 #define bRxSettle_AntSW 0xc0000 868 #define bRxProcessTime_DAGC 0x300000 869 #define bRxSettle_HSSI 0x400000 870 #define bRxProcessTime_BBPPW 0x800000 871 #define bRxAntennaPowerShift 0x3000000 872 #define bRSSITableSelect 0xc000000 873 #define bRxHP_Final 0x7000000 874 #define bRxHTSettle_BBP 0x7 875 #define bRxHTSettle_HSSI 0x8 876 #define bRxHTSettle_RxHP 0x70 877 #define bRxHTSettle_BBPPW 0x80 878 #define bRxHTSettle_Idle 0x300 879 #define bRxHTSettle_Reserved 0x1c00 880 #define bRxHTRxHPEn 0x8000 881 #define bRxHTAGCFreezeThres 0x30000 882 #define bRxHTAGCTogetherEn 0x40000 883 #define bRxHTAGCMin 0x80000 884 #define bRxHTAGCEn 0x100000 885 #define bRxHTDAGCEn 0x200000 886 #define bRxHTRxHP_BBP 0x1c00000 887 #define bRxHTRxHP_Final 0xe0000000 888 #define bRxPWRatioTH 0x3 889 #define bRxPWRatioEn 0x4 890 #define bRxMFHold 0x3800 891 #define bRxPD_Delay_TH1 0x38 892 #define bRxPD_Delay_TH2 0x1c0 893 #define bRxPD_DC_COUNT_MAX 0x600 894 /* define bRxMF_Hold 0x3800 */ 895 #define bRxPD_Delay_TH 0x8000 896 #define bRxProcess_Delay 0xf0000 897 #define bRxSearchrange_GI2_Early 0x700000 898 #define bRxFrame_Guard_Counter_L 0x3800000 899 #define bRxSGI_Guard_L 0xc000000 900 #define bRxSGI_Search_L 0x30000000 901 #define bRxSGI_TH 0xc0000000 902 #define bDFSCnt0 0xff 903 #define bDFSCnt1 0xff00 904 #define bDFSFlag 0xf0000 905 #define bMFWeightSum 0x300000 906 #define bMinIdxTH 0x7f000000 907 #define bDAFormat 0x40000 908 #define bTxChEmuEnable 0x01000000 909 #define bTRSWIsolation_A 0x7f 910 #define bTRSWIsolation_B 0x7f00 911 #define bTRSWIsolation_C 0x7f0000 912 #define bTRSWIsolation_D 0x7f000000 913 #define bExtLNAGain 0x7c00 914 915 /* 6. PageE(0xE00) */ 916 #define bSTBCEn 0x4 /* Useless */ 917 #define bAntennaMapping 0x10 918 #define bNss 0x20 919 #define bCFOAntSumD 0x200 920 #define bPHYCounterReset 0x8000000 921 #define bCFOReportGet 0x4000000 922 #define bOFDMContinueTx 0x10000000 923 #define bOFDMSingleCarrier 0x20000000 924 #define bOFDMSingleTone 0x40000000 925 /* define bRxPath1 0x01 */ 926 /* define bRxPath2 0x02 */ 927 /* define bRxPath3 0x04 */ 928 /* define bRxPath4 0x08 */ 929 /* define bTxPath1 0x10 */ 930 /* define bTxPath2 0x20 */ 931 #define bHTDetect 0x100 932 #define bCFOEn 0x10000 933 #define bCFOValue 0xfff00000 934 #define bSigTone_Re 0x3f 935 #define bSigTone_Im 0x7f00 936 #define bCounter_CCA 0xffff 937 #define bCounter_ParityFail 0xffff0000 938 #define bCounter_RateIllegal 0xffff 939 #define bCounter_CRC8Fail 0xffff0000 940 #define bCounter_MCSNoSupport 0xffff 941 #define bCounter_FastSync 0xffff 942 #define bShortCFO 0xfff 943 #define bShortCFOTLength 12 /* total */ 944 #define bShortCFOFLength 11 /* fraction */ 945 #define bLongCFO 0x7ff 946 #define bLongCFOTLength 11 947 #define bLongCFOFLength 11 948 #define bTailCFO 0x1fff 949 #define bTailCFOTLength 13 950 #define bTailCFOFLength 12 951 #define bmax_en_pwdB 0xffff 952 #define bCC_power_dB 0xffff0000 953 #define bnoise_pwdB 0xffff 954 #define bPowerMeasTLength 10 955 #define bPowerMeasFLength 3 956 #define bRx_HT_BW 0x1 957 #define bRxSC 0x6 958 #define bRx_HT 0x8 959 #define bNB_intf_det_on 0x1 960 #define bIntf_win_len_cfg 0x30 961 #define bNB_Intf_TH_cfg 0x1c0 962 #define bRFGain 0x3f 963 #define bTableSel 0x40 964 #define bTRSW 0x80 965 #define bRxSNR_A 0xff 966 #define bRxSNR_B 0xff00 967 #define bRxSNR_C 0xff0000 968 #define bRxSNR_D 0xff000000 969 #define bSNREVMTLength 8 970 #define bSNREVMFLength 1 971 #define bCSI1st 0xff 972 #define bCSI2nd 0xff00 973 #define bRxEVM1st 0xff0000 974 #define bRxEVM2nd 0xff000000 975 #define bSIGEVM 0xff 976 #define bPWDB 0xff00 977 #define bSGIEN 0x10000 978 979 #define bSFactorQAM1 0xf /* Useless */ 980 #define bSFactorQAM2 0xf0 981 #define bSFactorQAM3 0xf00 982 #define bSFactorQAM4 0xf000 983 #define bSFactorQAM5 0xf0000 984 #define bSFactorQAM6 0xf0000 985 #define bSFactorQAM7 0xf00000 986 #define bSFactorQAM8 0xf000000 987 #define bSFactorQAM9 0xf0000000 988 #define bCSIScheme 0x100000 989 990 #define bNoiseLvlTopSet 0x3 /* Useless */ 991 #define bChSmooth 0x4 992 #define bChSmoothCfg1 0x38 993 #define bChSmoothCfg2 0x1c0 994 #define bChSmoothCfg3 0xe00 995 #define bChSmoothCfg4 0x7000 996 #define bMRCMode 0x800000 997 #define bTHEVMCfg 0x7000000 998 999 #define bLoopFitType 0x1 /* Useless */ 1000 #define bUpdCFO 0x40 1001 #define bUpdCFOOffData 0x80 1002 #define bAdvUpdCFO 0x100 1003 #define bAdvTimeCtrl 0x800 1004 #define bUpdClko 0x1000 1005 #define bFC 0x6000 1006 #define bTrackingMode 0x8000 1007 #define bPhCmpEnable 0x10000 1008 #define bUpdClkoLTF 0x20000 1009 #define bComChCFO 0x40000 1010 #define bCSIEstiMode 0x80000 1011 #define bAdvUpdEqz 0x100000 1012 #define bUChCfg 0x7000000 1013 #define bUpdEqz 0x8000000 1014 1015 /* Rx Pseduo noise */ 1016 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 1017 #define bRxPesudoNoise_A 0xff 1018 #define bRxPesudoNoise_B 0xff00 1019 #define bRxPesudoNoise_C 0xff0000 1020 #define bRxPesudoNoise_D 0xff000000 1021 #define bPesudoNoiseState_A 0xffff 1022 #define bPesudoNoiseState_B 0xffff0000 1023 #define bPesudoNoiseState_C 0xffff 1024 #define bPesudoNoiseState_D 0xffff0000 1025 1026 /* 7. RF Register */ 1027 /* Zebra1 */ 1028 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1029 #define bZebra1_TRxControl 0xc00 1030 #define bZebra1_TRxGainSetting 0x07f 1031 #define bZebra1_RxCorner 0xc00 1032 #define bZebra1_TxChargePump 0x38 1033 #define bZebra1_RxChargePump 0x7 1034 #define bZebra1_ChannelNum 0xf80 1035 #define bZebra1_TxLPFBW 0x400 1036 #define bZebra1_RxLPFBW 0x600 1037 1038 /* Zebra4 */ 1039 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1040 #define bRTL8256RegModeCtrl0 0x40 1041 #define bRTL8256_TxLPFBW 0x18 1042 #define bRTL8256_RxLPFBW 0x600 1043 1044 /* RTL8258 */ 1045 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1046 #define bRTL8258_RxLPFBW 0xc00 1047 #define bRTL8258_RSSILPFBW 0xc0 1048 1049 1050 /* */ 1051 /* Other Definition */ 1052 /* */ 1053 1054 /* byte endable for sb_write */ 1055 #define bByte0 0x1 /* Useless */ 1056 #define bByte1 0x2 1057 #define bByte2 0x4 1058 #define bByte3 0x8 1059 #define bWord0 0x3 1060 #define bWord1 0xc 1061 #define bDWord 0xf 1062 1063 /* for PutRegsetting & GetRegSetting BitMask */ 1064 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1065 #define bMaskByte1 0xff00 1066 #define bMaskByte2 0xff0000 1067 #define bMaskByte3 0xff000000 1068 #define bMaskHWord 0xffff0000 1069 #define bMaskLWord 0x0000ffff 1070 #define bMaskDWord 0xffffffff 1071 #define bMaskH3Bytes 0xffffff00 1072 #define bMask12Bits 0xfff 1073 #define bMaskH4Bits 0xf0000000 1074 #define bMaskOFDM_D 0xffc00000 1075 #define bMaskCCK 0x3f3f3f3f 1076 1077 1078 #define bEnable 0x1 /* Useless */ 1079 #define bDisable 0x0 1080 1081 #define LeftAntenna 0x0 /* Useless */ 1082 #define RightAntenna 0x1 1083 1084 #define tCheckTxStatus 500 /* 500ms Useless */ 1085 #define tUpdateRxCounter 100 /* 100ms */ 1086 1087 #define rateCCK 0 /* Useless */ 1088 #define rateOFDM 1 1089 #define rateHT 2 1090 1091 /* define Register-End */ 1092 #define bPMAC_End 0x1ff /* Useless */ 1093 #define bFPGAPHY0_End 0x8ff 1094 #define bFPGAPHY1_End 0x9ff 1095 #define bCCKPHY0_End 0xaff 1096 #define bOFDMPHY0_End 0xcff 1097 #define bOFDMPHY1_End 0xdff 1098 1099 /* define max debug item in each debug page */ 1100 /* define bMaxItem_FPGA_PHY0 0x9 */ 1101 /* define bMaxItem_FPGA_PHY1 0x3 */ 1102 /* define bMaxItem_PHY_11B 0x16 */ 1103 /* define bMaxItem_OFDM_PHY0 0x29 */ 1104 /* define bMaxItem_OFDM_PHY1 0x0 */ 1105 1106 #define bPMACControl 0x0 /* Useless */ 1107 #define bWMACControl 0x1 1108 #define bWNICControl 0x2 1109 1110 #define PathA 0x0 /* Useless */ 1111 #define PathB 0x1 1112 #define PathC 0x2 1113 #define PathD 0x3 1114 1115 /*--------------------------Define Parameters-------------------------------*/ 1116 1117 1118 #endif /* __INC_HAL8192SPHYREG_H */ 1119
