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Searched refs:RENDER_RING_BASE (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dmmio_context.c49 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
50 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
51 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
52 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
53 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
54 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
[all …]
Dhandlers.c1836 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1895 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); in init_generic_mmio_info()
/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_gt.c65 clear_register(uncore, IPEIR(RENDER_RING_BASE)); in intel_gt_clear_error_registers()
213 RING_HEAD(RENDER_RING_BASE)); in intel_gt_flush_ggtt_writes()
Dintel_engine_cs.c76 { .gen = 1, .base = RENDER_RING_BASE }
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_cmd_parser.c603 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
661 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
668 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
Dintel_uncore.c915 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
925 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */
1808 .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
1809 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
Di915_gpu_error.c1548 error->ccid = intel_uncore_read(uncore, CCID(RENDER_RING_BASE)); in capture_reg_state()
Di915_reg.h2390 #define RENDER_RING_BASE 0x02000 macro
2410 #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
2411 #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
2412 #define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))