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Searched refs:REG_WAIT (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_dmcu.c81 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_dmcu_load_iram()
105 REG_WAIT(DCI_MEM_PWR_STATUS, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dce_get_dmcu_psr_state()
129 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_set_psr_enable()
223 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_dmcu_setup_psr()
300 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000); in dce_psr_wait_loop()
332 REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); in dcn10_get_dmcu_version()
354 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_enable_fractional_pwm()
367 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_enable_fractional_pwm()
389 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_init()
405 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 800); in dcn10_dmcu_init()
[all …]
Ddce_abm.c66 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_pipe()
192 REG_WAIT(BL_PWM_GRP1_REG_LOCK, in driver_set_backlight_level()
216 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
244 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, in dmcu_set_backlight_level()
317 REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, in dce_abm_set_level()
Ddce_aux.c125 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 1, in acquire_engine()
136 REG_WAIT(AUX_CONTROL, AUX_RESET_DONE, 0, in acquire_engine()
200 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0, in submit_channel_request()
329 REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1, in get_channel_status()
Ddce_mem_input.c597 REG_WAIT(DMIF_BUFFER_CONTROL, in dce_mi_allocate_dmif()
634 REG_WAIT(DMIF_BUFFER_CONTROL, in dce_mi_free_dmif()
Ddce_stream_encoder.c91 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in dce110_update_generic_info_packet()
735 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, in dce110_stream_encoder_set_mst_bandwidth()
954 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in dce110_stream_encoder_dp_blank()
Ddce_opp.c500 REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10); in program_formatter_reset_dig_resync_fifo()
Ddce_transform.c201 REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10); in program_multi_taps_filter()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c271 REG_WAIT(DOMAIN16_PG_STATUS, in dcn20_dsc_pg_control()
279 REG_WAIT(DOMAIN17_PG_STATUS, in dcn20_dsc_pg_control()
287 REG_WAIT(DOMAIN18_PG_STATUS, in dcn20_dsc_pg_control()
295 REG_WAIT(DOMAIN19_PG_STATUS, in dcn20_dsc_pg_control()
303 REG_WAIT(DOMAIN20_PG_STATUS, in dcn20_dsc_pg_control()
311 REG_WAIT(DOMAIN21_PG_STATUS, in dcn20_dsc_pg_control()
343 REG_WAIT(DOMAIN1_PG_STATUS, in dcn20_dpp_pg_control()
351 REG_WAIT(DOMAIN3_PG_STATUS, in dcn20_dpp_pg_control()
359 REG_WAIT(DOMAIN5_PG_STATUS, in dcn20_dpp_pg_control()
367 REG_WAIT(DOMAIN7_PG_STATUS, in dcn20_dpp_pg_control()
[all …]
Ddcn20_optc.c319 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc2_triplebuffer_lock()
Ddcn20_stream_encoder.c237 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc2_update_gsp7_128_info_packet()
Ddcn20_mpc.c440 REG_WAIT(MPCC_STATUS[id], in mpc2_assert_idle_mpcc()
Ddcn20_hubp.c928 REG_WAIT(DCHUBP_CNTL, in hubp2_set_blank()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c80 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc1_update_generic_info_packet()
645 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, in enc1_stream_encoder_set_mst_bandwidth()
770 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, in enc1_stream_encoder_send_immediate_sdp_message()
783 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, in enc1_stream_encoder_send_immediate_sdp_message()
826 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, in enc1_stream_encoder_send_immediate_sdp_message()
914 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, in enc1_stream_encoder_dp_blank()
Ddcn10_optc.c416 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL, in optc1_enable_optc_clock()
424 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_enable_optc_clock()
484 REG_WAIT(OTG_CLOCK_CONTROL, in optc1_disable_crtc()
604 REG_WAIT(OTG_MASTER_UPDATE_LOCK, in optc1_lock()
759 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
765 REG_WAIT(OTG_STATUS, in optc1_wait_for_state()
Ddcn10_hw_sequencer.c514 REG_WAIT(DOMAIN1_PG_STATUS, in dcn10_dpp_pg_control()
522 REG_WAIT(DOMAIN3_PG_STATUS, in dcn10_dpp_pg_control()
530 REG_WAIT(DOMAIN5_PG_STATUS, in dcn10_dpp_pg_control()
538 REG_WAIT(DOMAIN7_PG_STATUS, in dcn10_dpp_pg_control()
566 REG_WAIT(DOMAIN0_PG_STATUS, in dcn10_hubp_pg_control()
574 REG_WAIT(DOMAIN2_PG_STATUS, in dcn10_hubp_pg_control()
582 REG_WAIT(DOMAIN4_PG_STATUS, in dcn10_hubp_pg_control()
590 REG_WAIT(DOMAIN6_PG_STATUS, in dcn10_hubp_pg_control()
Ddcn10_mpc.c101 REG_WAIT(MPCC_STATUS[id], in mpc1_assert_idle_mpcc()
Ddcn10_hubp.c60 REG_WAIT(DCHUBP_CNTL, in hubp1_set_blank()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr_vbios_smu.c82 REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000); in rv1_vbios_smu_send_msg_with_param()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr_vbios_smu.c67 REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000); in rn_vbios_smu_send_msg_with_param()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubbub.c80 REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100); in dcn21_dchvm_init()
97 REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100); in dcn21_dchvm_init()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c129 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); in update_global_dpp_clk()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h218 #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \ macro