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Searched refs:REG_SET_2 (Results 1 – 25 of 29) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_dscl.c107 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0, in dpp1_dscl_set_overscan()
111 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0, in dpp1_dscl_set_overscan()
124 REG_SET_2(OTG_H_BLANK, 0, in dpp1_dscl_set_otg_blank()
128 REG_SET_2(OTG_V_BLANK, 0, in dpp1_dscl_set_otg_blank()
224 REG_SET_2(LB_DATA_FORMAT, 0, in dpp1_dscl_set_lb()
230 REG_SET_2(LB_MEMORY_CTRL, 0, in dpp1_dscl_set_lb()
388 REG_SET_2(SCL_MODE, scl_mode, in dpp1_dscl_set_scl_filter()
560 REG_SET_2(SCL_BLACK_OFFSET, 0, in dpp1_dscl_set_scaler_auto_scale()
565 REG_SET_2(SCL_BLACK_OFFSET, 0, in dpp1_dscl_set_scaler_auto_scale()
602 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in dpp1_dscl_set_manual_ratio_init()
[all …]
Ddcn10_hubp.c584 REG_SET_2(BLANK_OFFSET_0, 0, in hubp1_program_deadline()
594 REG_SET_2(DST_AFTER_SCALER, 0, in hubp1_program_deadline()
619 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp1_program_deadline()
641 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp1_program_deadline()
686 REG_SET_2(PREFETCH_SETTINS, 0, in hubp1_setup_interdependent()
693 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp1_setup_interdependent()
703 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp1_setup_interdependent()
716 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp1_setup_interdependent()
760 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_system_aperture_settings()
800 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubp1_set_vm_context0_settings()
[all …]
Ddcn10_cm_common.c56 REG_SET_2(cur_csc_reg, 0, in cm_helper_program_color_matrices()
73 REG_SET_2(reg->start_cntl_b, 0, in cm_helper_program_xfer_func()
76 REG_SET_2(reg->start_cntl_g, 0, in cm_helper_program_xfer_func()
79 REG_SET_2(reg->start_cntl_r, 0, in cm_helper_program_xfer_func()
92 REG_SET_2(reg->start_end_cntl2_b, 0, in cm_helper_program_xfer_func()
98 REG_SET_2(reg->start_end_cntl2_g, 0, in cm_helper_program_xfer_func()
104 REG_SET_2(reg->start_end_cntl2_r, 0, in cm_helper_program_xfer_func()
Ddcn10_optc.c82 REG_SET_2(OTG_VUPDATE_PARAM, 0, in optc1_program_global_sync()
97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0, in optc1_disable_stereo()
109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0, in optc1_setup_vertical_interrupt0()
799 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0, in optc1_set_static_screen_control()
1042 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern()
1054 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0, in optc1_set_test_pattern()
Ddcn10_stream_encoder.c430 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, in enc1_stream_encoder_dp_set_stream_attribute()
454 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, in enc1_stream_encoder_dp_set_stream_attribute()
469 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, in enc1_stream_encoder_dp_set_stream_attribute()
638 REG_SET_2(DP_MSE_RATE_CNTL, 0, in enc1_stream_encoder_set_mst_bandwidth()
Ddcn10_dpp_cm.c520 REG_SET_2(CM_BNS_VALUES_R, 0, in dpp1_program_bias_and_scale()
524 REG_SET_2(CM_BNS_VALUES_G, 0, in dpp1_program_bias_and_scale()
528 REG_SET_2(CM_BNS_VALUES_B, 0, in dpp1_program_bias_and_scale()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_opp.c90 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator()
151 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_set_disp_pattern_generator()
154 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_set_disp_pattern_generator()
157 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_set_disp_pattern_generator()
262 REG_SET_2(DPG_DIMENSIONS, 0, in opp2_set_disp_pattern_generator()
281 REG_SET_2(DPG_COLOUR_B_CB, 0, in opp2_dpg_set_blank_color()
284 REG_SET_2(DPG_COLOUR_G_Y, 0, in opp2_dpg_set_blank_color()
287 REG_SET_2(DPG_COLOUR_R_CR, 0, in opp2_dpg_set_blank_color()
Ddcn20_dpp_cm.c430 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
433 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
436 REG_SET_2(CM_SHAPER_RAMA_START_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
440 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_B, 0, in dpp20_program_shaper_luta_settings()
444 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_G, 0, in dpp20_program_shaper_luta_settings()
448 REG_SET_2(CM_SHAPER_RAMA_END_CNTL_R, 0, in dpp20_program_shaper_luta_settings()
580 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
583 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_G, 0, in dpp20_program_shaper_lutb_settings()
586 REG_SET_2(CM_SHAPER_RAMB_START_CNTL_R, 0, in dpp20_program_shaper_lutb_settings()
590 REG_SET_2(CM_SHAPER_RAMB_END_CNTL_B, 0, in dpp20_program_shaper_lutb_settings()
[all …]
Ddcn20_dccg.c76 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
80 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
85 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, in dccg2_update_dpp_dto()
Ddcn20_hubp.c72 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp2_set_vm_system_aperture_settings()
85 REG_SET_2(BLANK_OFFSET_0, 0, in hubp2_program_deadline()
95 REG_SET_2(DST_AFTER_SCALER, 0, in hubp2_program_deadline()
120 REG_SET_2(PER_LINE_DELIVERY, 0, in hubp2_program_deadline()
142 REG_SET_2(DCN_TTU_QOS_WM, 0, in hubp2_program_deadline()
247 REG_SET_2(PREFETCH_SETTINGS, 0, in hubp2_setup_interdependent()
254 REG_SET_2(VBLANK_PARAMETERS_0, 0, in hubp2_setup_interdependent()
258 REG_SET_2(FLIP_PARAMETERS_0, 0, in hubp2_setup_interdependent()
271 REG_SET_2(PER_LINE_DELIVERY_PRE, 0, in hubp2_setup_interdependent()
286 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0, in hubp2_setup_interdependent()
[all …]
Ddcn20_stream_encoder.c173 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
183 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
193 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
203 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
Ddcn20_dsc.c532 REG_SET_2(DSCCIF_CONFIG1, 0, in dsc_write_to_registers()
574 REG_SET_2(DSCC_PPS_CONFIG2, 0, in dsc_write_to_registers()
578 REG_SET_2(DSCC_PPS_CONFIG3, 0, in dsc_write_to_registers()
585 REG_SET_2(DSCC_PPS_CONFIG5, 0, in dsc_write_to_registers()
594 REG_SET_2(DSCC_PPS_CONFIG7, 0, in dsc_write_to_registers()
598 REG_SET_2(DSCC_PPS_CONFIG8, 0, in dsc_write_to_registers()
602 REG_SET_2(DSCC_PPS_CONFIG9, 0, in dsc_write_to_registers()
Ddcn20_optc.c124 REG_SET_2(OTG_GSL_WINDOW_X, 0, in optc2_set_gsl_window()
127 REG_SET_2(OTG_GSL_WINDOW_Y, 0, in optc2_set_gsl_window()
178 REG_SET_2(OTG_DSC_START_POSITION, 0, in optc2_set_dsc_encoder_frame_start()
Ddcn20_vmid.c85 REG_SET_2(CNTL, 0, in dcn20_vmid_setup()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_transform.c131 REG_SET_2(SCL_TAP_CONTROL, 0, in setup_scaling_configuration()
172 REG_SET_2(EXT_OVERSCAN_LEFT_RIGHT, 0, in program_overscan()
175 REG_SET_2(EXT_OVERSCAN_TOP_BOTTOM, 0, in program_overscan()
239 REG_SET_2(VIEWPORT_START, 0, in program_viewport()
243 REG_SET_2(VIEWPORT_SIZE, 0, in program_viewport()
293 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, in program_scl_ratios_inits()
297 REG_SET_2(SCL_VERT_FILTER_INIT, 0, in program_scl_ratios_inits()
331 REG_SET_2(LB_MEMORY_CTRL, 0, in dce_transform_set_scaler()
443 REG_SET_2(OUT_CLAMP_CONTROL_B_CB, 0, in set_clamp()
447 REG_SET_2(OUT_CLAMP_CONTROL_G_Y, 0, in set_clamp()
[all …]
Ddce_opp.c330 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
338 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
343 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
348 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
354 REG_SET_2(FMT_CLAMP_CNTL, 0, in dce110_opp_set_clamping()
359 REG_SET_2(FMT_CLAMP_COMPONENT_R, 0, in dce110_opp_set_clamping()
363 REG_SET_2(FMT_CLAMP_COMPONENT_G, 0, in dce110_opp_set_clamping()
367 REG_SET_2(FMT_CLAMP_COMPONENT_B, 0, in dce110_opp_set_clamping()
Ddce_ipp.c57 REG_SET_2(CUR_POSITION, 0, in dce_ipp_cursor_set_position()
61 REG_SET_2(CUR_HOT_SPOT, 0, in dce_ipp_cursor_set_position()
119 REG_SET_2(CUR_SIZE, 0, in dce_ipp_cursor_set_attributes()
149 REG_SET_2(PRESCALE_VALUES_GRPH_R, 0, in dce_ipp_program_prescale()
153 REG_SET_2(PRESCALE_VALUES_GRPH_G, 0, in dce_ipp_program_prescale()
157 REG_SET_2(PRESCALE_VALUES_GRPH_B, 0, in dce_ipp_program_prescale()
Ddce_hwseq.c71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
Ddce_mem_input.c172 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in program_urgency_watermark()
186 REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0, in dce120_program_urgency_watermark()
190 REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0, in dce120_program_urgency_watermark()
451 REG_SET_2(GRPH_SWAP_CNTL, 0, in program_grph_pixel_format()
657 REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0, in program_sec_addr()
Ddce_stream_encoder.c468 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, in dce110_stream_encoder_dp_set_stream_attribute()
495 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, in dce110_stream_encoder_dp_set_stream_attribute()
512 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, in dce110_stream_encoder_dp_set_stream_attribute()
727 REG_SET_2(DP_MSE_RATE_CNTL, 0, in dce110_stream_encoder_set_mst_bandwidth()
Ddce_i2c_hw.c248 value = REG_SET_2(DC_I2C_DATA, 0, in process_transaction()
256 REG_SET_2(DC_I2C_DATA, value, in process_transaction()
Ddce_aux.c227 value = REG_SET_2(AUX_SW_DATA, value, in submit_channel_request()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubbub.c138 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub21_program_urgent_watermarks()
169 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub21_program_urgent_watermarks()
200 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub21_program_urgent_watermarks()
231 REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub21_program_urgent_watermarks()
275 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks()
290 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub21_program_stutter_watermarks()
306 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks()
321 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub21_program_stutter_watermarks()
337 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks()
352 REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub21_program_stutter_watermarks()
[all …]
Ddcn21_hubp.c187 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0, in hubp21_set_vm_system_aperture_settings()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_ddc.c101 REG_SET_2(gpio.MASK_reg, regval, in set_config()

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