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Searched refs:REG_SET (Results 1 – 25 of 56) sorted by relevance

123

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.c386 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
390 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
395 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
399 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
415 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
419 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, in hubp1_program_surface_flip_and_addr()
423 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, in hubp1_program_surface_flip_and_addr()
427 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, in hubp1_program_surface_flip_and_addr()
432 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, in hubp1_program_surface_flip_and_addr()
436 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, in hubp1_program_surface_flip_and_addr()
[all …]
Ddcn10_mpc.c54 REG_SET(MPCC_BG_R_CR[mpcc_id], 0, in mpc1_set_bg_color()
56 REG_SET(MPCC_BG_G_Y[mpcc_id], 0, in mpc1_set_bg_color()
58 REG_SET(MPCC_BG_B_CB[mpcc_id], 0, in mpc1_set_bg_color()
209 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); in mpc1_insert_plane()
213 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf); in mpc1_insert_plane()
216 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id); in mpc1_insert_plane()
217 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id); in mpc1_insert_plane()
231 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id); in mpc1_insert_plane()
297 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
301 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, in mpc1_remove_mpcc()
[all …]
Ddcn10_dpp_cm.c120 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, in program_gamut_remap()
174 REG_SET( in program_gamut_remap()
221 REG_SET(CM_TEST_DEBUG_INDEX, 0, in dpp1_cm_program_color_matrix()
255 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode); in dpp1_cm_program_color_matrix()
343 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp1_cm_power_on_regamma_lut()
356 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg); in dpp1_cm_program_regamma_lut()
357 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg); in dpp1_cm_program_regamma_lut()
358 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg); in dpp1_cm_program_regamma_lut()
360 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg); in dpp1_cm_program_regamma_lut()
361 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg); in dpp1_cm_program_regamma_lut()
[all …]
Ddcn10_optc.c79 REG_SET(OTG_VSTARTUP_PARAM, 0, in optc1_program_global_sync()
86 REG_SET(OTG_VREADY_PARAM, 0, in optc1_program_global_sync()
94 REG_SET(OTG_STEREO_CONTROL, 0, in optc1_disable_stereo()
120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0, in optc1_setup_vertical_interrupt1()
130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0, in optc1_setup_vertical_interrupt2()
172 REG_SET(OTG_H_TOTAL, 0, in optc1_program_timing()
203 REG_SET(OTG_V_TOTAL, 0, in optc1_program_timing()
209 REG_SET(OTG_V_TOTAL_MAX, 0, in optc1_program_timing()
211 REG_SET(OTG_V_TOTAL_MIN, 0, in optc1_program_timing()
596 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc1_lock()
[all …]
Ddcn10_hubbub.c318 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, in hubbub1_program_urgent_watermarks()
341 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, in hubbub1_program_urgent_watermarks()
364 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, in hubbub1_program_urgent_watermarks()
387 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, in hubbub1_program_urgent_watermarks()
423 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
437 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, in hubbub1_program_stutter_watermarks()
452 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
466 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, in hubbub1_program_stutter_watermarks()
481 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
495 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, in hubbub1_program_stutter_watermarks()
[all …]
Ddcn10_opp.c98 REG_SET(FMT_DITHER_RAND_R_SEED, 0, in opp1_set_spatial_dither()
101 REG_SET(FMT_DITHER_RAND_G_SEED, 0, in opp1_set_spatial_dither()
104 REG_SET(FMT_DITHER_RAND_B_SEED, 0, in opp1_set_spatial_dither()
Ddcn10_cm_common.c83 REG_SET(reg->start_slope_cntl_b, 0, in cm_helper_program_xfer_func()
85 REG_SET(reg->start_slope_cntl_g, 0, in cm_helper_program_xfer_func()
87 REG_SET(reg->start_slope_cntl_r, 0, in cm_helper_program_xfer_func()
90 REG_SET(reg->start_end_cntl1_b, 0, in cm_helper_program_xfer_func()
96 REG_SET(reg->start_end_cntl1_g, 0, in cm_helper_program_xfer_func()
102 REG_SET(reg->start_end_cntl1_r, 0, in cm_helper_program_xfer_func()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubp.c63 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, in hubp2_set_vm_system_aperture_settings()
66 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp2_set_vm_system_aperture_settings()
69 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp2_set_vm_system_aperture_settings()
89 REG_SET(BLANK_OFFSET_1, 0, in hubp2_program_deadline()
92 REG_SET(DST_DIMENSIONS, 0, in hubp2_program_deadline()
99 REG_SET(REF_FREQ_TO_PIX_FREQ, 0, in hubp2_program_deadline()
103 REG_SET(VBLANK_PARAMETERS_1, 0, in hubp2_program_deadline()
107 REG_SET(NOM_PARAMETERS_0, 0, in hubp2_program_deadline()
111 REG_SET(NOM_PARAMETERS_1, 0, in hubp2_program_deadline()
114 REG_SET(NOM_PARAMETERS_4, 0, in hubp2_program_deadline()
[all …]
Ddcn20_vmid.c75 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
77 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
80 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
82 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
89 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
92 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
Ddcn20_optc.c198 REG_SET(OPTC_BYTES_PER_PIXEL, 0, in optc2_set_dsc_config()
227 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_bypass()
250 REG_SET(OPTC_MEMORY_CONFIG, 0, in optc2_set_odm_combine()
269 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); in optc2_set_odm_combine()
309 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc2_triplebuffer_lock()
312 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_lock()
315 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_triplebuffer_lock()
328 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc2_triplebuffer_unlock()
331 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc2_triplebuffer_unlock()
378 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, in optc2_setup_manual_trigger()
[all …]
Ddcn20_mpc.c63 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); in mpc2_update_blending()
64 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); in mpc2_update_blending()
65 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); in mpc2_update_blending()
138 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_output_csc()
177 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); in mpc2_set_ocsc_default()
242 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0, in mpc20_power_on_ogam_lut()
257 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); in mpc20_configure_ogam_lut()
349 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); in mpc20_program_ogam_pwl()
350 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg); in mpc20_program_ogam_pwl()
351 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg); in mpc20_program_ogam_pwl()
[all …]
Ddcn20_dpp_cm.c99 REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0); in dpp2_program_degamma_lut()
101 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg); in dpp2_program_degamma_lut()
102 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg); in dpp2_program_degamma_lut()
103 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg); in dpp2_program_degamma_lut()
105 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
107 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
109 REG_SET(CM_DGAM_LUT_DATA, 0, in dpp2_program_degamma_lut()
164 REG_SET(CM_MEM_PWR_CTRL, 0, in dpp20_power_on_blnd_lut()
179 REG_SET(CM_BLNDGAM_LUT_INDEX, 0, CM_BLNDGAM_LUT_INDEX, 0); in dpp20_configure_blnd_lut()
191 REG_SET(CM_BLNDGAM_LUT_DATA, 0, CM_BLNDGAM_LUT_DATA, rgb[i].red_reg); in dpp20_program_blnd_pwl()
[all …]
Ddcn20_hubbub.c370 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub2_init_dchub_sys_ctx()
372 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub2_init_dchub_sys_ctx()
374 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub2_init_dchub_sys_ctx()
376 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub2_init_dchub_sys_ctx()
378 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub2_init_dchub_sys_ctx()
380 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub2_init_dchub_sys_ctx()
383 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0, in hubbub2_init_dchub_sys_ctx()
385 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0, in hubbub2_init_dchub_sys_ctx()
587 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, in hubbub2_program_watermarks()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_ipp.c129 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0, in dce_ipp_cursor_set_attributes()
132 REG_SET(CUR_SURFACE_ADDRESS, 0, in dce_ipp_cursor_set_attributes()
180 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1); in dce_ipp_program_input_lut()
183 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7); in dce_ipp_program_input_lut()
195 REG_SET(DC_LUT_RW_INDEX, 0, in dce_ipp_program_input_lut()
199 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
202 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
205 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, in dce_ipp_program_input_lut()
212 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0); in dce_ipp_program_input_lut()
Ddce_transform.c120 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0); in setup_scaling_configuration()
144 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1); in setup_scaling_configuration()
199 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1); in program_multi_taps_filter()
287 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
290 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, in program_scl_ratios_inits()
358 REG_SET(SCL_VERT_FILTER_CONTROL, 0, in dce_transform_set_scaler()
373 REG_SET(SCL_HORZ_FILTER_CONTROL, 0, in dce_transform_set_scaler()
538 REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits); in set_round()
744 REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode); in set_denormalization()
824 REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1); in program_gamut_remap()
[all …]
Ddce_mem_input.c413 REG_SET(GRPH_X_START, 0, in program_size_and_rotation()
416 REG_SET(GRPH_Y_START, 0, in program_size_and_rotation()
419 REG_SET(GRPH_X_END, 0, in program_size_and_rotation()
422 REG_SET(GRPH_Y_END, 0, in program_size_and_rotation()
425 REG_SET(GRPH_PITCH, 0, in program_size_and_rotation()
428 REG_SET(HW_ROTATION, 0, in program_size_and_rotation()
594 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, in dce_mi_allocate_dmif()
631 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control, in dce_mi_free_dmif()
653 REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0, in program_sec_addr()
667 REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0, in program_pri_addr()
[all …]
Ddce_aux.c231 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
235 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
248 value = REG_SET(AUX_SW_DATA, value, in submit_channel_request()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubp.c80 REG_SET(VBLANK_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
87 REG_SET(VBLANK_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
92 REG_SET(FLIP_PARAMETERS_3, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
97 REG_SET(FLIP_PARAMETERS_4, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
100 REG_SET(FLIP_PARAMETERS_5, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
102 REG_SET(FLIP_PARAMETERS_6, 0, in apply_DEDCN21_142_wa_for_hostvm_deadline()
181 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
184 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0, in hubp21_set_vm_system_aperture_settings()
Ddcn21_hubbub.c105 REG_SET(DCN_VM_FB_LOCATION_BASE, 0, in hubbub21_init_dchub()
107 REG_SET(DCN_VM_FB_LOCATION_TOP, 0, in hubbub21_init_dchub()
109 REG_SET(DCN_VM_FB_OFFSET, 0, in hubbub21_init_dchub()
111 REG_SET(DCN_VM_AGP_BOT, 0, in hubbub21_init_dchub()
113 REG_SET(DCN_VM_AGP_TOP, 0, in hubbub21_init_dchub()
115 REG_SET(DCN_VM_AGP_BASE, 0, in hubbub21_init_dchub()
152 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, in hubbub21_program_urgent_watermarks()
160 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, in hubbub21_program_urgent_watermarks()
183 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, in hubbub21_program_urgent_watermarks()
191 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, in hubbub21_program_urgent_watermarks()
[all …]
/Linux-v5.4/arch/arm/mach-imx/
Danatop.c16 #define REG_SET 0x4 macro
50 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
56 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
62 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
68 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/Linux-v5.4/drivers/thermal/
Dimx_thermal.c26 #define REG_SET 0x4 macro
233 regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET, in imx_set_panic_temp()
253 regmap_write(map, soc_data->high_alarm_ctrl + REG_SET, in imx_set_alarm_temp()
278 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_get_temp()
296 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_get_temp()
364 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_set_mode()
374 regmap_write(map, soc_data->sensor_ctrl + REG_SET, in imx_set_mode()
733 regmap_write(map, data->socdata->low_alarm_ctrl + REG_SET, in imx_thermal_probe()
769 regmap_write(map, IMX6_MISC0 + REG_SET, in imx_thermal_probe()
771 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_ddc.c119 REG_SET(gpio.MASK_reg, regval, in set_config()
128 REG_SET(gpio.MASK_reg, regval, in set_config()
166 REG_SET(gpio.MASK_reg, regval, in set_config()
/Linux-v5.4/drivers/gpu/drm/radeon/
Dr300d.h61 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
62 REG_SET(PACKET0_COUNT, (n)))
63 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
65 REG_SET(PACKET3_IT_OPCODE, (op)) | \
66 REG_SET(PACKET3_COUNT, (n)))
Drv515d.h201 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
202 REG_SET(PACKET0_COUNT, (n)))
203 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
205 REG_SET(PACKET3_IT_OPCODE, (op)) | \
206 REG_SET(PACKET3_COUNT, (n)))
/Linux-v5.4/drivers/gpu/drm/mxsfb/
Dmxsfb_crtc.c128 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); in mxsfb_enable_controller()
135 writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); in mxsfb_enable_controller()
224 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); in mxsfb_crtc_mode_set_nofb()

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