Home
last modified time | relevance | path

Searched refs:REG_FIELD_PREP (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_lvds.c213 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | in intel_lvds_pps_init_hw()
214 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | in intel_lvds_pps_init_hw()
215 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); in intel_lvds_pps_init_hw()
218 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | in intel_lvds_pps_init_hw()
219 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); in intel_lvds_pps_init_hw()
222 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | in intel_lvds_pps_init_hw()
223 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, in intel_lvds_pps_init_hw()
Dintel_dp.c6568 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in intel_dp_init_panel_power_sequencer_registers()
6569 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); in intel_dp_init_panel_power_sequencer_registers()
6570 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in intel_dp_init_panel_power_sequencer_registers()
6571 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in intel_dp_init_panel_power_sequencer_registers()
6604 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | in intel_dp_init_panel_power_sequencer_registers()
6605 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); in intel_dp_init_panel_power_sequencer_registers()
6611 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); in intel_dp_init_panel_power_sequencer_registers()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_reg.h162 #define REG_FIELD_PREP(__mask, __val) \ macro
4724 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0)
4725 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1)
4726 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2)
4729 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0)
4730 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1)
4731 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2)
4732 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3)
4733 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8)
4734 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9)
[all …]
Di915_irq.c478 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); in gen11_enable_guc_interrupts()