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Searched refs:REG_FIELD_MASK (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c5768 REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
5769 REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
5771 REG_FIELD_MASK(CPC_EDC_UCODE_CNT, SEC_COUNT),
5772 REG_FIELD_MASK(CPC_EDC_UCODE_CNT, DED_COUNT) },
5774 REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME1), 0 },
5776 REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME2), 0 },
5778 REG_FIELD_MASK(CPF_EDC_TAG_CNT, SEC_COUNT),
5779 REG_FIELD_MASK(CPF_EDC_TAG_CNT, DED_COUNT) },
5781 REG_FIELD_MASK(CPG_EDC_DMA_CNT, ROQ_COUNT), 0 },
5783 REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
[all …]
Dsoc15_common.h33 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
124 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
Dmxgpu_vi.c321 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_send_ack()
368 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID); in xgpu_vi_mailbox_rcv_msg()
390 u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, TRN_MSG_ACK); in xgpu_vi_poll_ack()
Damdgpu.h1109 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK macro
1112 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1113 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1116 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1119 …WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, fi…
1122 …WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_F…
/Linux-v5.4/drivers/misc/habanalabs/
Dhabanalabs.h1050 #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK macro
1052 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | \