Searched refs:REG_DSI_28nm_PHY_PLL_SDM_CFG1 (Results 1 – 2 of 2) sorted by relevance
184 sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); in dsi_pll_28nm_clk_set_rate()216 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1); in dsi_pll_28nm_clk_set_rate()281 pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1), in dsi_pll_28nm_clk_recalc_rate()
1023 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c macro
