Searched refs:REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG (Results 1 – 2 of 2) sorted by relevance
144 pll_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); in dsi_pll_28nm_clk_set_rate()
1004 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024 macro
