Searched refs:REG_DSI_28nm_PHY_PLL_EFUSE_CFG (Results 1 – 2 of 2) sorted by relevance
238 pll_write(base + REG_DSI_28nm_PHY_PLL_EFUSE_CFG, 0x20); in dsi_pll_28nm_clk_set_rate()
1096 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c macro
