Searched refs:REG_DSI_28nm_8960_PHY_PLL_CTRL_8 (Results 1 – 2 of 2) sorted by relevance
143 val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); in dsi_pll_28nm_clk_set_rate()145 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, in dsi_pll_28nm_clk_set_rate()310 val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); in dsi_pll_28nm_enable_seq()313 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, val); in dsi_pll_28nm_enable_seq()348 pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); in dsi_pll_28nm_save_state()372 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8, in dsi_pll_28nm_restore_state()
771 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020 macro
