Searched refs:REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 (Results 1 – 2 of 2) sorted by relevance
534 pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data); in pll_db_commit_14nm()644 div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) in dsi_pll_14nm_vco_recalc_rate()
1531 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4 macro
