Home
last modified time | relevance | path

Searched refs:REG_CLR_BIT (Results 1 – 17 of 17) sorted by relevance

/Linux-v5.4/drivers/net/wireless/ath/ath9k/
Dar9002_calib.c447 REG_CLR_BIT(ah, AR9285_AN_RF2G6, 1 << 0); in ar9271_hw_pa_cal()
459 REG_CLR_BIT(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL); in ar9271_hw_pa_cal()
461 REG_CLR_BIT(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB); in ar9271_hw_pa_cal()
463 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL); in ar9271_hw_pa_cal()
465 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1); in ar9271_hw_pa_cal()
467 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2); in ar9271_hw_pa_cal()
469 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT); in ar9271_hw_pa_cal()
522 REG_CLR_BIT(ah, 0x9808, 1 << 27); in ar9271_hw_pa_cal()
723 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
725 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
[all …]
Dar9003_wow.c54 REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE); in ath9k_hw_set_powermode_wow_sleep()
58 REG_CLR_BIT(ah, AR_DIRECT_CONNECT, AR_DC_TSF2_ENABLE); in ath9k_hw_set_powermode_wow_sleep()
316 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PMCTRL_WOW_PME_CLR); in ath9k_hw_wow_enable()
389 REG_CLR_BIT(ah, AR_WOW_BCN_EN, AR_WOW_BEACON_FAIL_EN); in ath9k_hw_wow_enable()
438 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_wow_enable()
449 REG_CLR_BIT(ah, AR_PCU_MISC_MODE3, BIT(5)); in ath9k_hw_wow_enable()
Dar9002_phy.c215 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate()
219 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate()
484 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
499 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, repeat_bit); in ar9002_hw_spectral_scan_config()
559 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9002_hw_tx99_start()
Dar9003_phy.c831 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
833 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
835 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
1157 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1460 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar9003_hw_set_radar_params()
1485 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1649 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1651 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1653 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1655 REG_CLR_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
[all …]
Dcalib.c234 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
285 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf()
294 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
296 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_loadnf()
Dmac.c162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); in ath9k_hw_abort_tx_dma()
163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma()
164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); in ath9k_hw_abort_tx_dma()
649 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
661 REG_CLR_BIT(ah, AR_DIAG_SW, in ath9k_hw_setrxabort()
681 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ath9k_hw_startpcureceive()
1021 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); in ath9k_hw_set_interrupts()
Dar9003_calib.c349 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
351 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_dynamic_osdac_selection()
372 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_dynamic_osdac_selection()
374 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
376 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
402 REG_CLR_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_dynamic_osdac_selection()
534 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
1445 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_init_cal_pcoem()
1472 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_init_cal_pcoem()
Dhw.c741 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
1287 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1415 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); in ath9k_hw_set_reset()
1697 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
2104 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2105 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2106 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep()
2116 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep()
2126 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); in ath9k_set_power_sleep()
2162 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, in ath9k_set_power_network_sleep()
[all …]
Drng.c38 REG_CLR_BIT(ah, AR_PHY_TEST, AR_PHY_TEST_RX_OBS_SEL_BIT5); in ath9k_rng_data_read()
Dar9003_mci.c766 REG_CLR_BIT(ah, AR_PHY_TIMING4, in ar9003_mci_end_reset()
820 REG_CLR_BIT(ah, AR_BTCOEX_CTRL, in ar9003_mci_osla_setup()
1018 REG_CLR_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_reset()
1142 REG_CLR_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_2g5g_switch()
1144 REG_CLR_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_2g5g_switch()
1452 REG_CLR_BIT(ah, AR_BTCOEX_RC, 0x1); in ar9003_mci_set_power_awake()
Dar9002_hw.c252 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
377 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
Dar9003_paprd.c316 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1, in ar9003_get_desired_gain()
815 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1, in ar9003_paprd_setup_gain_table()
935 REG_CLR_BIT(ah, AR_PHY_CHAN_INFO_MEMORY, in ar9003_paprd_create_curve()
954 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1, in ar9003_paprd_create_curve()
Dbtcoex.c176 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_2wire()
331 REG_CLR_BIT(ah, AR_BT_COEX_MODE2, AR_BT_PHY_ERR_BT_COLL_ENABLE); in ath9k_hw_btcoex_enable_3wire()
Dar9003_aic.c254 REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE); in ar9003_aic_cal_start()
509 REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE); in ar9003_aic_cal_continue()
Dar5008_phy.c1006 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1216 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar5008_hw_set_radar_params()
1241 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
Dhw.h129 #define REG_CLR_BIT(_a, _r, _f) \ macro
Dar9003_eeprom.c3753 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_ant_ctrl_apply()
3757 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_ant_ctrl_apply()