Searched refs:REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR (Results 1 – 2 of 2) sorted by relevance
478 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); in a6xx_gmu_rpmh_init()481 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); in a6xx_gmu_rpmh_init()484 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080); in a6xx_gmu_rpmh_init()
5232 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 macro
