Searched refs:RD_REG_DWORD (Results 1 – 14 of 14) sorted by relevance
146 stat = RD_REG_DWORD(®->host_status); in qla27xx_dump_mpi_ram()157 RD_REG_DWORD(®->hccr); in qla27xx_dump_mpi_ram()164 RD_REG_DWORD(®->hccr); in qla27xx_dump_mpi_ram()223 stat = RD_REG_DWORD(®->host_status); in qla24xx_dump_ram()233 RD_REG_DWORD(®->hccr); in qla24xx_dump_ram()240 RD_REG_DWORD(®->hccr); in qla24xx_dump_ram()296 *buf++ = htonl(RD_REG_DWORD(dmp_reg)); in qla24xx_read_window()308 if (RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) in qla24xx_pause_risc()327 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_soft_reset()332 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_soft_reset()[all …]
370 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)380 RD_REG_DWORD((ha)->cregbase + off)386 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)399 RD_REG_DWORD((ha)->cregbase + off)
687 RD_REG_DWORD(®->rsp_q_out); in qlafx00_config_rings()916 pseudo_aen = RD_REG_DWORD(®->pseudoaen); in qlafx00_init_fw_ready()918 aenmbx7 = RD_REG_DWORD(®->initval7); in qlafx00_init_fw_ready()929 aenmbx = RD_REG_DWORD(®->aenmailbox0); in qlafx00_init_fw_ready()948 aenmbx7 = RD_REG_DWORD(®->aenmailbox7); in qlafx00_init_fw_ready()951 ha->req_que_off = RD_REG_DWORD(®->aenmailbox1); in qlafx00_init_fw_ready()952 ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3); in qlafx00_init_fw_ready()953 ha->req_que_len = RD_REG_DWORD(®->aenmailbox5); in qlafx00_init_fw_ready()954 ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6); in qlafx00_init_fw_ready()986 aenmbx7 = RD_REG_DWORD(®->initval7); in qlafx00_init_fw_ready()[all …]
462 if (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) { in qla24xx_read_flash_dword()463 *data = RD_REG_DWORD(®->flash_data); in qla24xx_read_flash_dword()506 if (!(RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG)) in qla24xx_write_flash_dword()1201 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_unprotect_flash()1202 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_unprotect_flash()1244 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_protect_flash()1470 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()1471 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()1494 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()1495 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()[all …]
373 win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_pci_set_crbwindow_2M()523 data = RD_REG_DWORD(off); in qla82xx_rd_32()943 RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_md_rw_32()950 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M + in qla82xx_md_rw_32()2073 if (RD_REG_DWORD(®->host_int)) { in qla82xx_intr_handler()2074 stat = RD_REG_DWORD(®->host_status); in qla82xx_intr_handler()2139 host_int = RD_REG_DWORD(®->host_int); in qla82xx_msix_default()2143 stat = RD_REG_DWORD(®->host_status); in qla82xx_msix_default()2200 host_int = RD_REG_DWORD(®->host_int); in qla82xx_msix_rsp_q()2235 host_int = RD_REG_DWORD(®->host_int); in qla82xx_poll()[all …]
190 stat = RD_REG_DWORD(®->u.isp2300.host_status); in qla2300_intr_handler()3112 RD_REG_DWORD(®->iobase_addr); in qla2xxx_check_risc_status()3114 for (cnt = 10000; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()3127 for (cnt = 100; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()3139 if (RD_REG_DWORD(®->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()3145 RD_REG_DWORD(®->iobase_window); in qla2xxx_check_risc_status()3189 stat = RD_REG_DWORD(®->host_status); in qla24xx_intr_handler()3196 hccr = RD_REG_DWORD(®->hccr); in qla24xx_intr_handler()3318 stat = RD_REG_DWORD(®->host_status); in qla24xx_msix_default()3325 hccr = RD_REG_DWORD(®->hccr); in qla24xx_msix_default()
2180 if (RD_REG_DWORD(®->mailbox12) & BIT_0) { in qla2x00_initialize_adapter()2428 ha->pci_attr = RD_REG_DWORD(®->ctrl_status); in qla24xx_pci_config()2687 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_reset_risc()2693 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_reset_risc()2698 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()2699 RD_REG_DWORD(®->ctrl_status), in qla24xx_reset_risc()2700 (RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)); in qla24xx_reset_risc()2724 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()2725 RD_REG_DWORD(®->mailbox0)); in qla24xx_reset_risc()2728 RD_REG_DWORD(®->ctrl_status); in qla24xx_reset_risc()[all …]
304 if (RD_REG_DWORD(®->isp82.hint) & in qla2x00_mailbox_command()422 ictrl = RD_REG_DWORD(®->isp24.ictrl); in qla2x00_mailbox_command()423 host_status = RD_REG_DWORD(®->isp24.host_status); in qla2x00_mailbox_command()424 hccr = RD_REG_DWORD(®->isp24.hccr); in qla2x00_mailbox_command()577 RD_REG_DWORD(®->isp24.host_status), in qla2x00_mailbox_command()578 RD_REG_DWORD(®->isp24.ictrl), in qla2x00_mailbox_command()579 RD_REG_DWORD(®->isp24.istatus)); in qla2x00_mailbox_command()5287 stat = RD_REG_DWORD(®->host_status); in qla81xx_write_mpi_register()5298 RD_REG_DWORD(®->hccr); in qla81xx_write_mpi_register()
2269 cnt = RD_REG_DWORD(®->isp25mq.req_q_out); in __qla2x00_alloc_iocbs()2271 cnt = RD_REG_DWORD(®->isp82.req_q_out); in __qla2x00_alloc_iocbs()2273 cnt = RD_REG_DWORD(®->isp24.req_q_out); in __qla2x00_alloc_iocbs()2275 cnt = RD_REG_DWORD(®->ispfx00.req_q_out); in __qla2x00_alloc_iocbs()3360 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { in qla82xx_start_scsi()
1220 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT); in qla2x00_isp_reg_stat()1222 return ((RD_REG_DWORD(®->host_status)) == in qla2x00_isp_reg_stat()1905 RD_REG_DWORD(®->ictrl); in qla24xx_enable_intrs()1920 RD_REG_DWORD(®->ictrl); in qla24xx_disable_intrs()6956 stat = RD_REG_DWORD(®->hccr); in qla2xxx_pci_mmio_enabled()6960 stat = RD_REG_DWORD(®->u.isp2300.host_status); in qla2xxx_pci_mmio_enabled()6964 stat = RD_REG_DWORD(®24->host_status); in qla2xxx_pci_mmio_enabled()
72 value = RD_REG_DWORD(window); in qla27xx_read32()
3949 if (RD_REG_DWORD(®->host_int)) { in qla8044_intr_handler()3950 stat = RD_REG_DWORD(®->host_status); in qla8044_intr_handler()
130 #define RD_REG_DWORD(addr) readl(addr) macro
6812 RD_REG_DWORD(ISP_ATIO_Q_OUT(vha)); in qlt_24xx_config_rings()
