Searched refs:RADEON_PPLL_REF_DIV (Results 1 – 4 of 4) sorted by relevance
224 RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); in radeon_pll_wait_for_read_update_complete()232 while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); in radeon_pll_write_update()234 WREG32_PLL_P(RADEON_PPLL_REF_DIV, in radeon_pll_write_update()934 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && in radeon_set_pll()971 WREG32_PLL_P(RADEON_PPLL_REF_DIV, in radeon_set_pll()976 WREG32_PLL_P(RADEON_PPLL_REF_DIV, in radeon_set_pll()981 WREG32_PLL_P(RADEON_PPLL_REF_DIV, in radeon_set_pll()
121 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_read_clocks_OF()199 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); in radeon_get_clock_info()241 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_get_clock_info()
1578 #define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ macro
1155 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; in radeon_legacy_get_lvds_info_from_regs()
