Searched refs:QSPI (Results 1 – 25 of 27) sorted by relevance
12
1 * STMicroelectronics Quad Serial Peripheral Interface(QSPI)9 - clocks: the phandle of the clock needed by the QSPI controller10 - A pinctrl must be defined to set pins in mode of operation for QSPI transfer19 - reg: chip-Select number (QSPI controller may connect 2 flashes)35 resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;36 clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
1 TI QSPI controller.5 - reg: Should contain QSPI registers location and length.12 - ti,hwmods: Name of the hwmod associated to the QSPI19 - syscon-chipselects: Handle to system control region contains QSPI22 NOTE: TI QSPI controller requires different pinmux and IODelay26 specified in the slave nodes of TI QSPI controller without appropriate
1 Xilinx Zynq QSPI controller Device Tree Bindings6 - reg : Physical base address and size of QSPI registers map.
1 * Atmel Quad Serial Peripheral Interface (QSPI)13 - clocks: Should reference the peripheral clock and the QSPI system
1 Qualcomm Quad Serial Peripheral Interface (QSPI)3 The QSPI controller allows SPI protocol communication in single, dual, or quad
1 Device tree configuration for Renesas RSPI/QSPI driver
152 label = "QSPI.SPL";156 label = "QSPI.SPL.backup1";160 label = "QSPI.SPL.backup2";164 label = "QSPI.SPL.backup3";168 label = "QSPI.u-boot";172 label = "QSPI.u-boot-spl-os";176 label = "QSPI.u-boot-env";180 label = "QSPI.u-boot-env.backup1";184 label = "QSPI.kernel";188 label = "QSPI.file-system";
472 label = "QSPI.SPL";476 label = "QSPI.SPL.backup1";480 label = "QSPI.SPL.backup2";484 label = "QSPI.SPL.backup3";488 label = "QSPI.u-boot";492 label = "QSPI.u-boot-spl-os";496 label = "QSPI.u-boot-env";500 label = "QSPI.u-boot-env.backup1";504 label = "QSPI.kernel";508 label = "QSPI.file-system";
460 label = "QSPI.SPL";464 label = "QSPI.u-boot";468 label = "QSPI.u-boot-spl-os";472 label = "QSPI.u-boot-env";476 label = "QSPI.u-boot-env.backup1";480 label = "QSPI.kernel";484 label = "QSPI.file-system";
288 label = "QSPI.u-boot-spl-os";292 label = "QSPI.u-boot-env";296 label = "QSPI.skern";300 label = "QSPI.pmmc-firmware";304 label = "QSPI.kernel";308 label = "QSPI.file-system";
343 label = "QSPI.u-boot";347 label = "QSPI.u-boot-env";351 label = "QSPI.skern";355 label = "QSPI.pmmc-firmware";359 label = "QSPI.kernel";363 label = "QSPI.u-boot-spl-os";367 label = "QSPI.file-system";
456 label = "QSPI.U_BOOT";460 label = "QSPI.U_BOOT.backup";464 label = "QSPI.U-BOOT-SPL_OS";468 label = "QSPI.U_BOOT_ENV";472 label = "QSPI.U-BOOT-ENV.backup";476 label = "QSPI.KERNEL";480 label = "QSPI.FILESYSTEM";
742 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */885 status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */907 label = "QSPI.U_BOOT";911 label = "QSPI.U_BOOT.backup";915 label = "QSPI.U-BOOT-SPL_OS";919 label = "QSPI.U_BOOT_ENV";923 label = "QSPI.U-BOOT-ENV.backup";927 label = "QSPI.KERNEL";931 label = "QSPI.FILESYSTEM";
756 label = "QSPI.U_BOOT";760 label = "QSPI.U_BOOT.backup";764 label = "QSPI.U-BOOT-SPL_OS";768 label = "QSPI.U_BOOT_ENV";772 label = "QSPI.U-BOOT-ENV.backup";776 label = "QSPI.KERNEL";780 label = "QSPI.FILESYSTEM";
11 address and length of the QSPI Controller data area.20 - cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch21 the read data rather than the QSPI clock. Make sure that QSPI return
14 - Dual mode QSPI
337 QSPI, enumerator429 INTC_VECT(QSPI, 0xE60),437 INTC_GROUP(SPI, HSPI, RSPI, QSPI),
203 tristate "Freescale Coldfire QSPI controller"206 This enables support for the Coldfire QSPI controller in master273 tristate "Freescale QSPI controller"491 tristate "DRA7xxx QSPI controller support"494 QSPI master controller for DRA7xxx used for flash devices.572 tristate "Renesas RSPI/QSPI controller"575 SPI driver for Renesas RSPI and QSPI blocks.578 tristate "QTI QSPI controller"581 QSPI(Quad SPI) driver for Qualcomm QSPI controller.866 tristate "Xilinx Zynq QSPI controller"
43 Cadence QSPI is a specialized controller for connecting an SPI45 device with a Cadence QSPI controller and want to access the
120 #define QSPI 107 macro
17 the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
1387 …PINGROUP(qspi_sck_pee0, QSPI, RSVD1, RSVD2, RSVD3, 0x3088, Y, Y, N, 0x…1388 …PINGROUP(qspi_cs_n_pee1, QSPI, RSVD1, RSVD2, RSVD3, 0x308c, Y, Y, N, -1…1389 …PINGROUP(qspi_io0_pee2, QSPI, RSVD1, RSVD2, RSVD3, 0x3090, Y, Y, N, -1…1390 …PINGROUP(qspi_io1_pee3, QSPI, RSVD1, RSVD2, RSVD3, 0x3094, Y, Y, N, -1…1391 …PINGROUP(qspi_io2_pee4, QSPI, RSVD1, RSVD2, RSVD3, 0x3098, Y, Y, N, -1…1392 …PINGROUP(qspi_io3_pee5, QSPI, RSVD1, RSVD2, RSVD3, 0x309c, Y, Y, N, -1…
117 QSPI FIFO ECC121 - altr,ecc-parent : phandle to parent QSPI node.
