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Searched refs:PP_CONTROL (Results 1 – 12 of 12) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/gma500/
Dpsb_lid.c28 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
44 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
Dpsb_intel_lvds.c219 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
230 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
264 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); in psb_intel_lvds_save()
315 REG_WRITE(PP_CONTROL, lvds_priv->savePP_CONTROL); in psb_intel_lvds_restore()
319 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_restore()
325 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_restore()
Dcdv_intel_dp.c391 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
394 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_on()
395 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
405 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
408 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_vdd_off()
409 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
424 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
428 REG_WRITE(PP_CONTROL, pp); in cdv_intel_edp_panel_on()
429 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
449 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
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Doaktrail_lvds.c44 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in oaktrail_lvds_set_power()
55 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in oaktrail_lvds_set_power()
Dcdv_intel_lvds.c196 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
207 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
Doaktrail_device.c233 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); in oaktrail_save_display_registers()
262 PSB_WVDC32(0, PP_CONTROL); in oaktrail_save_display_registers()
370 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); in oaktrail_restore_display_registers()
Dcdv_device.c278 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); in cdv_save_display_registers()
357 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); in cdv_restore_display_registers()
Dpsb_intel_reg.h168 #define PP_CONTROL 0x61204 macro
/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_lvds.c159 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
206 val = I915_READ(PP_CONTROL(0)); in intel_lvds_pps_init_hw()
210 I915_WRITE(PP_CONTROL(0), val); in intel_lvds_pps_init_hw()
318 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
334 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); in intel_disable_lvds()
Dintel_dp.c912 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; in vlv_pipe_has_vdd_on()
1034 regs->pp_ctrl = PP_CONTROL(pps_idx); in intel_pps_get_registers()
1085 pp_ctrl_reg = PP_CONTROL(pipe); in edp_notify_handler()
Dintel_display.c1198 pp_reg = PP_CONTROL(0); in assert_panel_unlocked()
1220 pp_reg = PP_CONTROL(pipe); in assert_panel_unlocked()
1225 pp_reg = PP_CONTROL(0); in assert_panel_unlocked()
15296 u32 val = I915_READ(PP_CONTROL(pps_idx)); in intel_pps_unlock_regs_wa()
15299 I915_WRITE(PP_CONTROL(pps_idx), val); in intel_pps_unlock_regs_wa()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_reg.h4740 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) macro