Searched refs:PPLL_POST3_DIV_MASK (Results 1 – 4 of 4) sorted by relevance
270 #define PPLL_POST3_DIV_MASK 0x70000 macro
995 #define PPLL_POST3_DIV_MASK 0x00070000 macro
1373 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { in radeon_write_pll_regs()1422 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
1349 div3 &= ~PPLL_POST3_DIV_MASK; in aty128_set_pll()