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Searched refs:PMC (Results 1 – 25 of 39) sorted by relevance

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/Linux-v5.4/arch/mips/pmcs-msp71xx/
DKconfig3 prompt "PMC-Sierra MSP SOC type"
7 bool "PMC-Sierra MSP4200 Eval Board"
13 bool "PMC-Sierra MSP4200 VoIP Gateway"
18 bool "PMC-Sierra MSP7120 Eval Board"
24 bool "PMC-Sierra MSP7120 Residential Gateway"
32 bool "PMC-Sierra MSP7120 FPGA"
DPlatform2 # PMC-Sierra MSP SOCs
/Linux-v5.4/drivers/video/fbdev/riva/
Dnvreg.h126 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
127 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
128 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
129 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130 #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
133 #define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
134 #define PMC_Read(reg) DEVICE_READ(PMC,reg)
135 #define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
136 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
[all …]
Dnv_driver.c167 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_memlen()
168 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) { in riva_get_memlen()
281 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in riva_get_maxdclk()
282 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) { in riva_get_maxdclk()
330 par->riva.PMC = in riva_common_setup()
Driva_hw.c1418 LOAD_FIXED_STATE(Riva,PMC); in LoadStateExt()
1572 NV_WR32(chip->PMC, 0x00008704, 1); in LoadStateExt()
1573 NV_WR32(chip->PMC, 0x00008140, 0); in LoadStateExt()
1574 NV_WR32(chip->PMC, 0x00008920, 0); in LoadStateExt()
1575 NV_WR32(chip->PMC, 0x00008924, 0); in LoadStateExt()
1576 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); in LoadStateExt()
1577 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); in LoadStateExt()
1578 NV_WR32(chip->PMC, 0x00001588, 0); in LoadStateExt()
1730 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); in LoadStateExt()
1987 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) in nv3GetConfig()
[all …]
Driva_hw.h452 volatile U032 __iomem *PMC; member
/Linux-v5.4/Documentation/devicetree/bindings/powerpc/fsl/
Dpmc.txt6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
8 whose PMC is compatible, and implies deep-sleep capability.
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
12 whose PMC is compatible, and implies deep-sleep capability.
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
23 is the PMC block, and the second resource is the Clock Configuration
30 resource is the PMC block interrupt.
/Linux-v5.4/Documentation/driver-api/xilinx/
Deemi.rst10 used by any driver to communicate with PMC(Platform Management Controller).
16 device to communicate with a power management controller (PMC) on a
21 structure. Any driver who want to communicate with PMC using EEMI APIs
/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dvt8500.txt16 - reg : shall be the control register offset from PMC base for the pll clock.
36 - enable-reg : shall be the register offset from PMC base for the enable
44 - divisor-reg : shall be the register offset from PMC base for the divisor
Dat91-clock.txt31 Power Management Controller (PMC):
/Linux-v5.4/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
5 The PMC block interacts with an external Power Management Unit. The PMC
28 signal is fed into the PMC. This signal is optionally inverted, and then
29 fed into the ARM GIC. The PMC is not involved in the detection or
39 - nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
130 that can be power-gated by the Tegra PMC. The name of the powergate node
161 - clocks: Must contain an entry for each clock required by the PMC for
163 - resets: Must contain an entry for each reset required by the PMC for
202 The pin grouping is a fixed attribute of the hardware. The PMC can be
Dnvidia,tegra186-pmc.txt1 NVIDIA Tegra Power Management Controller (PMC)
44 The pin grouping is a fixed attribute of the hardware. The PMC can be
/Linux-v5.4/drivers/video/fbdev/nvidia/
Dnv_hw.c147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
950 NV_WR32(par->PMC, 0x0140, 0x00000000); in NVLoadStateExt()
951 NV_WR32(par->PMC, 0x0200, 0xFFFF00FF); in NVLoadStateExt()
952 NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF); in NVLoadStateExt()
1266 NV_WR32(par->PMC, 0x1700, in NVLoadStateExt()
1268 NV_WR32(par->PMC, 0x1704, 0); in NVLoadStateExt()
1269 NV_WR32(par->PMC, 0x1708, 0); in NVLoadStateExt()
[all …]
Dnv_backlight.c63 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF; in nvidia_bl_update_status()
76 NV_WR32(par->PMC, 0x10F0, tmp_pmc); in nvidia_bl_update_status()
Dnv_setup.c237 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) { in nv10GetConfig()
238 NV_WR32(par->PMC, 0x0004, 0x01000001); in nv10GetConfig()
306 par->PMC = par->REGS + (0x00000000 / 4); in NVCommonSetup()
Dnv_type.h164 volatile u32 __iomem *PMC; member
/Linux-v5.4/arch/sparc/include/asm/
Dns87303.h20 #define PMC 0x06 macro
/Linux-v5.4/arch/powerpc/boot/dts/
Dxpedite5200_xmon.dts17 form-factor = "PMC/XMC";
108 * 6: PMC monarch indicator
109 * 7: PMC EREADY
445 /* PMC interface */
Dmvme5100.dts130 /* IDSEL 16 - PMC Slot 1 */
136 /* IDSEL 17 - PMC Slot 2 */
Dxpedite5200.dts104 * 6: PMC monarch indicator
105 * 7: PMC EREADY
442 /* PMC interface */
Dxpedite5301.dts6 * XPedite5301 PMC/XMC module based on MPC8572E
15 form-factor = "PMC/XMC";
601 /* PCI Express controller 1, wired to PEX8112 for PMC interface */
/Linux-v5.4/Documentation/devicetree/bindings/mfd/
Datmel-flexcom.txt11 - clocks: Should be the Flexcom peripheral clock from PMC.
/Linux-v5.4/drivers/scsi/smartpqi/
DKconfig7 # Copyright (c) 2016 PMC-Sierra, Inc.
/Linux-v5.4/Documentation/powerpc/
Dpmu-ebb.rst83 EBB events must specify the PMC they are to be counted on. This ensures
84 userspace is able to reliably determine which PMC the event is scheduled on.
/Linux-v5.4/drivers/net/can/sja1000/
DKconfig80 - esd CAN-PCI/PMC/266

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