Searched refs:PLL_ENABLE (Results 1 – 7 of 7) sorted by relevance
| /Linux-v5.4/drivers/clk/spear/ |
| D | clk-vco-pll.c | 50 #define PLL_ENABLE 2 macro
315 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
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| /Linux-v5.4/sound/soc/codecs/ |
| D | tlv320aic3x.c | 1091 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); in aic3x_hw_params()
1097 PLL_ENABLE, PLL_ENABLE); in aic3x_hw_params()
1454 PLL_ENABLE, PLL_ENABLE); in aic3x_set_bias_level()
1464 PLL_ENABLE, 0); in aic3x_set_bias_level()
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| D | tlv320aic3x.h | 210 #define PLL_ENABLE 0x80 macro
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| /Linux-v5.4/drivers/clk/tegra/ |
| D | clk-tegra210.c | 317 #define PLL_ENABLE (1 << 30) macro
708 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { in tegra210_pllcx_set_defaults()
761 if (val & PLL_ENABLE) { in tegra210_plla_set_defaults()
814 PLL_ENABLE) { in tegra210_plld_set_defaults()
867 if (val & PLL_ENABLE) { in plldss_defaults()
986 if (val & PLL_ENABLE) { in tegra210_pllre_set_defaults()
1111 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
1164 if (val & PLL_ENABLE) { in tegra210_pllmb_set_defaults()
1225 if (val & PLL_ENABLE) { in tegra210_pllp_set_defaults()
1288 if (val & PLL_ENABLE) { in tegra210_pllu_set_defaults()
[all …]
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| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.c | 2064 val |= PLL_ENABLE; in cnl_ddi_pll_enable()
2108 val &= ~PLL_ENABLE; in cnl_ddi_pll_disable()
2152 if (!(val & PLL_ENABLE)) in cnl_ddi_pll_get_hw_state()
3058 if (!(val & PLL_ENABLE)) in mg_pll_get_hw_state()
3120 if (!(val & PLL_ENABLE)) in icl_pll_get_hw_state()
3263 val |= PLL_ENABLE; in icl_pll_enable()
3358 val &= ~PLL_ENABLE; in icl_pll_disable()
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| /Linux-v5.4/drivers/clk/imx/ |
| D | clk-imx6q.c | 390 #define PLL_ENABLE BIT(13) macro
418 reg &= ~PLL_ENABLE; in disable_anatop_clocks()
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| /Linux-v5.4/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 9749 #define PLL_ENABLE (1 << 31) macro
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