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Searched refs:PLL_DIV (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/drivers/mfd/
Ddb8500-prcmu.c462 PLL_DIV enumerator
470 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
475 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
477 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
478 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
[all …]
/Linux-v5.4/drivers/clk/at91/
Dclk-pll.c19 #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK) macro
71 div = PLL_DIV(pllr); in clk_pll_prepare()
304 pll->div = PLL_DIV(pllr); in at91_clk_register_pll()
/Linux-v5.4/arch/mips/ar7/
Dclock.c54 #define PLL_DIV 0x00000002 macro
192 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { in tnetd7300_get_clock()