Searched refs:PIPECONF_ENABLE (Results 1 – 9 of 9) sorted by relevance
62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled()77 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()305 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
448 if (data & PIPECONF_ENABLE) in pipeconf_mmio_write()
286 #define PIPECONF_ENABLE (1 << 31) macro
1354 tmp &= ~PIPECONF_ENABLE; in intelfbhw_program_mode()1366 tmp &= ~PIPECONF_ENABLE; in intelfbhw_program_mode()1441 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE); in intelfbhw_program_mode()
897 tmp |= PIPECONF_ENABLE; in gen11_dsi_enable_transcoder()1077 tmp &= ~PIPECONF_ENABLE; in gen11_dsi_disable_transcoder()1334 ret = tmp & PIPECONF_ENABLE; in gen11_dsi_get_hw_state()
1027 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()1029 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()1043 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()1044 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
1259 cur_state = !!(val & PIPECONF_ENABLE); in assert_pipe()1831 if (val & PIPECONF_ENABLE) { in intel_enable_pipe()1837 I915_WRITE(reg, val | PIPECONF_ENABLE); in intel_enable_pipe()1872 if ((val & PIPECONF_ENABLE) == 0) in intel_disable_pipe()1884 val &= ~PIPECONF_ENABLE; in intel_disable_pipe()1887 if ((val & PIPECONF_ENABLE) == 0) in intel_disable_pipe()8289 pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()8787 if (!(tmp & PIPECONF_ENABLE)) in i9xx_get_pipe_config()9963 if (!(tmp & PIPECONF_ENABLE)) in ironlake_get_pipe_config()10293 return tmp & PIPECONF_ENABLE; in hsw_get_transcoder_state()[all …]
992 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
5622 #define PIPECONF_ENABLE (1 << 31) macro
