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Searched refs:PIPECONF (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Ddisplay.c62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE)) in edp_pipe_is_enabled()
77 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
305 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE; in emulate_monitor_status_change()
Dhandlers.c1964 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1965 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1966 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1967 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
/Linux-v5.4/drivers/gpu/drm/i915/display/
Dicl_dsi.c896 tmp = I915_READ(PIPECONF(dsi_trans)); in gen11_dsi_enable_transcoder()
898 I915_WRITE(PIPECONF(dsi_trans), tmp); in gen11_dsi_enable_transcoder()
901 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_enable_transcoder()
1076 tmp = I915_READ(PIPECONF(dsi_trans)); in gen11_dsi_disable_transcoder()
1078 I915_WRITE(PIPECONF(dsi_trans), tmp); in gen11_dsi_disable_transcoder()
1081 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), in gen11_dsi_disable_transcoder()
1333 tmp = I915_READ(PIPECONF(dsi_trans)); in gen11_dsi_get_hw_state()
Dintel_color.c432 val = I915_READ(PIPECONF(pipe)); in i9xx_color_commit()
435 I915_WRITE(PIPECONF(pipe), val); in i9xx_color_commit()
445 val = I915_READ(PIPECONF(pipe)); in ilk_color_commit()
448 I915_WRITE(PIPECONF(pipe), val); in ilk_color_commit()
Dintel_display.c1077 i915_reg_t reg = PIPECONF(cpu_transcoder); in intel_wait_for_pipe_off()
1258 u32 val = I915_READ(PIPECONF(cpu_transcoder)); in assert_pipe()
1646 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()
1692 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
1829 reg = PIPECONF(cpu_transcoder); in intel_enable_pipe()
1870 reg = PIPECONF(cpu_transcoder); in intel_disable_pipe()
4844 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
4916 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
4944 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
5270 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
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Dintel_crt.c661 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
Dintel_display_power.c1027 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1029 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1043 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && in i830_pipes_power_well_enabled()
1044 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
Dvlv_dsi.c992 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
Dintel_dp.c6704 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); in intel_dp_set_drrs_state()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_reg.h5740 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) macro