Searched refs:PHY_RESET (Results 1 – 12 of 12) sorted by relevance
| /Linux-v5.4/drivers/phy/hisilicon/ |
| D | phy-hix5hd2-sata.c | 20 #define PHY_RESET BIT(0) macro
84 REF_SSP_EN | PHY_RESET; in hix5hd2_sata_phy_init()
87 val &= ~PHY_RESET; in hix5hd2_sata_phy_init()
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| /Linux-v5.4/drivers/net/ethernet/qualcomm/emac/ |
| D | emac-sgmii.c | 186 writel(((val & ~PHY_RESET) | PHY_RESET), phy->base + in emac_sgmii_reset_prepare()
191 writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2); in emac_sgmii_reset_prepare()
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| D | emac.h | 172 #define PHY_RESET BIT(0) macro
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| /Linux-v5.4/drivers/phy/cadence/ |
| D | phy-cadence-dp.c | 34 #define PHY_RESET 0x20 macro
188 cdns_phy->base + PHY_RESET); in cdns_dp_phy_init()
198 cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1); in cdns_dp_phy_init()
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| /Linux-v5.4/drivers/net/dsa/ |
| D | bcm_sf2_regs.h | 46 #define PHY_RESET (1 << 5) macro
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| D | bcm_sf2.c | 93 reg |= PHY_RESET; in bcm_sf2_gphy_enable_set()
98 reg &= ~PHY_RESET; in bcm_sf2_gphy_enable_set()
100 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; in bcm_sf2_gphy_enable_set()
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | imx53-tqma53.dtsi | 83 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
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| /Linux-v5.4/drivers/net/dsa/microchip/ |
| D | ksz8795_reg.h | 758 #define PHY_RESET BIT(15) macro
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| D | ksz8795.c | 558 if (val & PHY_RESET) in ksz8795_w_phy()
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| /Linux-v5.4/drivers/net/usb/ |
| D | r8152.c | 621 PHY_RESET, enumerator
3377 set_bit(PHY_RESET, &tp->flags); in r8152b_hw_phy_cfg()
3616 set_bit(PHY_RESET, &tp->flags); in r8153_hw_phy_cfg()
3708 set_bit(PHY_RESET, &tp->flags); in r8153b_hw_phy_cfg()
3963 if (test_and_clear_bit(PHY_RESET, &tp->flags)) in rtl8152_set_speed()
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| /Linux-v5.4/drivers/scsi/aic94xx/ |
| D | aic94xx_reg_def.h | 1577 #define PHY_RESET 0x02 macro
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| /Linux-v5.4/drivers/net/ethernet/micrel/ |
| D | ksz884x.c | 277 #define PHY_RESET 0x8000 macro
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