Searched refs:PHYCLKPerState (Results 1 – 5 of 5) sorted by relevance
399 double PHYCLKPerState[DC__VOLTAGE_STATES + 1]; member
257 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
4051 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20_ModeSupportAndSystemConfigurationFull()4064 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml20_ModeSupportAndSystemConfigurationFull()4093 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml20_ModeSupportAndSystemConfigurationFull()4123 && mode_lib->vba.PHYCLKPerState[i] in dml20_ModeSupportAndSystemConfigurationFull()
4083 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20v2_ModeSupportAndSystemConfigurationFull()4096 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()4125 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml20v2_ModeSupportAndSystemConfigurationFull()4155 && mode_lib->vba.PHYCLKPerState[i] in dml20v2_ModeSupportAndSystemConfigurationFull()
4123 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml21_ModeSupportAndSystemConfigurationFull()4137 if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) { in dml21_ModeSupportAndSystemConfigurationFull()4168 if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) { in dml21_ModeSupportAndSystemConfigurationFull()4200 && mode_lib->vba.PHYCLKPerState[i] in dml21_ModeSupportAndSystemConfigurationFull()
