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Searched refs:PHASE (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.h61 SRII(PHASE, DP_DTO, 0),\
62 SRII(PHASE, DP_DTO, 1),\
63 SRII(PHASE, DP_DTO, 2),\
64 SRII(PHASE, DP_DTO, 3),\
65 SRII(PHASE, DP_DTO, 4),\
66 SRII(PHASE, DP_DTO, 5),\
84 SRII(PHASE, DP_DTO, 0),\
85 SRII(PHASE, DP_DTO, 1),\
86 SRII(PHASE, DP_DTO, 2),\
87 SRII(PHASE, DP_DTO, 3),\
[all …]
Ddce_clock_source.c915 REG_WRITE(PHASE[inst], clock_100hz); in dce112_program_pix_clk()
994 clock_hz = REG_READ(PHASE[inst]); in get_pixel_clk_frequency_100hz()
/Linux-v5.4/sound/firewire/
DKconfig104 * TerraTec PHASE 24 FW/PHASE X24 FW/PHASE 88 Rack FW
/Linux-v5.4/drivers/scsi/
DFlashPoint.c527 #define PHASE BIT(13) macro
1835 && !((RDW_HARPOON((ioport + hp_intstat)) & PHASE) in FlashPoint_HandleInterrupt()
1862 (PROG_HLT | RSEL | PHASE | BUS_FREE)); in FlashPoint_HandleInterrupt()
1898 (PHASE | IUNKWN | PROG_HLT)); in FlashPoint_HandleInterrupt()
2086 (PROG_HLT | TIMEOUT | SEL | BUS_FREE | PHASE | in FPT_SccbMgr_bad_isr()
2674 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2679 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2752 (PHASE | RESET)) in FPT_sres()
2834 while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) && in FPT_sres()
2844 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_SendMsg()
[all …]
/Linux-v5.4/Documentation/networking/
Dcan.rst1172 [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1
1173 phase-seg2 PHASE-SEG2 [ sjw SJW ] ]
1176 [ dtq TQ dprop-seg PROP_SEG dphase-seg1 PHASE-SEG1
1177 dphase-seg2 PHASE-SEG2 [ dsjw SJW ] ]
1195 PHASE-SEG1 := { 1..8 }
1196 PHASE-SEG2 := { 1..8 }
/Linux-v5.4/Documentation/scsi/
Dsym53c8xx_2.txt124 LOAD/STORE and handles PHASE MISMATCH from SCRIPTS for devices that
130 Chip SDMS BIOS Wide SCSI std. Max. sync SCRIPTS PHASE MISMATCH
DChangeLog.sym53c8xx341 to testing for a PHASE. SYMBIOS say this feature is working fine.
Dncr53c8xx.txt1012 have detected an expected disconnection (BUS FREE PHASE). For this process