Searched refs:PCLK1 (Results 1 – 3 of 3) sorted by relevance
4 #define PCLK1 2 macro
40 clocks = <&rcc PCLK1>, <&rcc SPI2_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>;
533 hws[PCLK1] = clk_hw_register_divider_table(NULL, "pclk1", "hclk", 0, in register_core_and_bus_clocks()
