Searched refs:PCH_DREF_CONTROL (Results 1 – 4 of 4) sorted by relevance
8943 val = I915_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()9001 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()9002 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()9017 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()9018 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()9028 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()9029 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()9042 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()9043 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()16170 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & in intel_modeset_init()
406 val = I915_READ(PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
2282 MMIO_D(PCH_DREF_CONTROL, D_ALL); in init_generic_mmio_info()
8076 #define PCH_DREF_CONTROL _MMIO(0xC6200) macro
