Searched refs:PACKET3_PREAMBLE_END_CLEAR_STATE (Results 1 – 19 of 19) sorted by relevance
255 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
207 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
209 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
271 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
389 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
1840 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
2075 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v6_0_cp_gfx_start()2915 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v6_0_get_csb_buffer()
2575 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()4028 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_get_csb_buffer()
958 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v10_0_get_csb_buffer()2707 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v10_0_cp_gfx_start()
1487 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()3180 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
1283 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()4242 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
1263 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
1777 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
1855 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
1658 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
1585 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cayman_cp_start()
3603 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in si_cp_start()5769 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in si_get_csb_buffer()
4021 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()6773 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_get_csb_buffer()
3034 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in evergreen_cp_start()
