Searched refs:NR_IRQS_LEGACY (Results 1 – 25 of 28) sorted by relevance
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119 #define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)120 #define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)121 #define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)122 #define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)123 #define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)124 #define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)125 #define MX27_INT_MSHC (NR_IRQS_LEGACY + 7)126 #define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)127 #define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)128 #define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)[all …]
90 #define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6)91 #define MX21_INT_GPIO (NR_IRQS_LEGACY + 8)92 #define MX21_INT_FIRI (NR_IRQS_LEGACY + 9)93 #define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10)94 #define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11)95 #define MX21_INT_I2C (NR_IRQS_LEGACY + 12)96 #define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13)97 #define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14)98 #define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15)99 #define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16)[all …]
125 #define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)126 #define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)127 #define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)128 #define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)129 #define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)130 #define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)131 #define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)132 #define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)133 #define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)134 #define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)[all …]
126 #define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3)127 #define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4)128 #define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5)129 #define MX31_INT_RTIC (NR_IRQS_LEGACY + 6)130 #define MX31_INT_FIRI (NR_IRQS_LEGACY + 7)131 #define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8)132 #define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9)133 #define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10)134 #define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11)135 #define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12)[all …]
59 #define MX2x_INT_CSPI3 (NR_IRQS_LEGACY + 6)60 #define MX2x_INT_GPIO (NR_IRQS_LEGACY + 8)61 #define MX2x_INT_SDHC2 (NR_IRQS_LEGACY + 10)62 #define MX2x_INT_SDHC1 (NR_IRQS_LEGACY + 11)63 #define MX2x_INT_I2C (NR_IRQS_LEGACY + 12)64 #define MX2x_INT_SSI2 (NR_IRQS_LEGACY + 13)65 #define MX2x_INT_SSI1 (NR_IRQS_LEGACY + 14)66 #define MX2x_INT_CSPI2 (NR_IRQS_LEGACY + 15)67 #define MX2x_INT_CSPI1 (NR_IRQS_LEGACY + 16)68 #define MX2x_INT_UART4 (NR_IRQS_LEGACY + 17)[all …]
143 #define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3)144 #define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4)145 #define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6)146 #define MX3x_INT_I2C (NR_IRQS_LEGACY + 10)147 #define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13)148 #define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14)149 #define MX3x_INT_ATA (NR_IRQS_LEGACY + 15)150 #define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18)151 #define MX3x_INT_IIM (NR_IRQS_LEGACY + 19)152 #define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22)[all …]
24 #define INT_CAMERA (NR_IRQS_LEGACY + 1)25 #define INT_FIQ (NR_IRQS_LEGACY + 3)26 #define INT_RTDX (NR_IRQS_LEGACY + 6)27 #define INT_DSP_MMU_ABORT (NR_IRQS_LEGACY + 7)28 #define INT_HOST (NR_IRQS_LEGACY + 8)29 #define INT_ABORT (NR_IRQS_LEGACY + 9)30 #define INT_BRIDGE_PRIV (NR_IRQS_LEGACY + 13)31 #define INT_GPIO_BANK1 (NR_IRQS_LEGACY + 14)32 #define INT_UART3 (NR_IRQS_LEGACY + 15)33 #define INT_TIMER3 (NR_IRQS_LEGACY + 16)[all …]
5 #define NR_IRQS_LEGACY 16 macro10 #define NR_IRQS NR_IRQS_LEGACY41 return NR_IRQS_LEGACY; in nr_legacy_irqs()
128 #define NR_IRQS_LEGACY 16 macro143 #define NR_IRQS NR_IRQS_LEGACY
147 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))207 #define gsi_top (NR_IRQS_LEGACY)
157 ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4; in ams_delta_init_fiq()197 offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4; in ams_delta_init_fiq()
236 omap_l2_irq -= NR_IRQS_LEGACY; in omap1_init_irq()
105 cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt?
27 #define NR_IRQS_LEGACY NUM_ISA_INTERRUPTS macro
12 #define NR_IRQS_LEGACY NR_IRQS_BASE macro
20 #define MX1_TIM1_INT (NR_IRQS_LEGACY + 59)
21 #define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26)
18 #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
21 #define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
15 #define PXA_IRQ(x) (NR_IRQS_LEGACY + (x))
411 .nr_legacy_irqs = NR_IRQS_LEGACY,
97 static u32 isa_irq_to_gsi[NR_IRQS_LEGACY] __read_mostly = {345 if (bus_irq >= NR_IRQS_LEGACY) { in mp_override_legacy_irq()478 if (bus_irq < NR_IRQS_LEGACY) in acpi_sci_ioapic_setup()
19 #define INT_DMA_LCD (NR_IRQS_LEGACY + 25)
534 #ifndef NR_IRQS_LEGACY535 # define NR_IRQS_LEGACY 0 macro
702 return NR_IRQS_LEGACY; in arch_probe_nr_irqs()
