Searched refs:MVPP22_XLG_CTRL0_REG (Results 1 – 2 of 2) sorted by relevance
1330 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1333 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1348 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()1350 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()1612 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & in mvpp2_mac_reset_assert()1614 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_reset_assert()4833 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp22_xlg_link_state()4912 old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()4932 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()4937 while (!(readl(port->base + MVPP22_XLG_CTRL0_REG) & in mvpp2_xlg_config()[all …]
457 #define MVPP22_XLG_CTRL0_REG 0x100 macro
