1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Marvell 88E6xxx Switch Global 2 Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11 #ifndef _MV88E6XXX_GLOBAL2_H
12 #define _MV88E6XXX_GLOBAL2_H
13
14 #include "chip.h"
15
16 /* Offset 0x00: Interrupt Source Register */
17 #define MV88E6XXX_G2_INT_SRC 0x00
18 #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
19 #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
20 #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
21 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
22 #define MV88E6352_G2_INT_SRC_SERDES 0x0800
23 #define MV88E6352_G2_INT_SRC_PHY 0x001f
24 #define MV88E6390_G2_INT_SRC_PHY 0x07fe
25
26 #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15
27
28 /* Offset 0x01: Interrupt Mask Register */
29 #define MV88E6XXX_G2_INT_MASK 0x01
30 #define MV88E6XXX_G2_INT_MASK_WDOG 0x8000
31 #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000
32 #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000
33 #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000
34 #define MV88E6352_G2_INT_MASK_SERDES 0x0800
35 #define MV88E6352_G2_INT_MASK_PHY 0x001f
36 #define MV88E6390_G2_INT_MASK_PHY 0x07fe
37
38 /* Offset 0x02: MGMT Enable Register 2x */
39 #define MV88E6XXX_G2_MGMT_EN_2X 0x02
40
41 /* Offset 0x03: MGMT Enable Register 0x */
42 #define MV88E6XXX_G2_MGMT_EN_0X 0x03
43
44 /* Offset 0x04: Flow Control Delay Register */
45 #define MV88E6XXX_G2_FLOW_CTL 0x04
46
47 /* Offset 0x05: Switch Management Register */
48 #define MV88E6XXX_G2_SWITCH_MGMT 0x05
49 #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000
50 #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000
51 #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000
52 #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080
53 #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008
54
55 /* Offset 0x06: Device Mapping Table Register */
56 #define MV88E6XXX_G2_DEVICE_MAPPING 0x06
57 #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000
58 #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00
59 #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f
60 #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f
61
62 /* Offset 0x07: Trunk Mask Table Register */
63 #define MV88E6XXX_G2_TRUNK_MASK 0x07
64 #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000
65 #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000
66 #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800
67
68 /* Offset 0x08: Trunk Mapping Table Register */
69 #define MV88E6XXX_G2_TRUNK_MAPPING 0x08
70 #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000
71 #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800
72
73 /* Offset 0x09: Ingress Rate Command Register */
74 #define MV88E6XXX_G2_IRL_CMD 0x09
75 #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000
76 #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000
77 #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000
78 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000
79 #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000
80 #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000
81 #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000
82 #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000
83 #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000
84 #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000
85 #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000
86 #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000
87 #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00
88 #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00
89 #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0
90 #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f
91
92 /* Offset 0x0A: Ingress Rate Data Register */
93 #define MV88E6XXX_G2_IRL_DATA 0x0a
94 #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff
95
96 /* Offset 0x0B: Cross-chip Port VLAN Register */
97 #define MV88E6XXX_G2_PVT_ADDR 0x0b
98 #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000
99 #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000
100 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000
101 #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000
102 #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000
103 #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff
104
105 /* Offset 0x0C: Cross-chip Port VLAN Data Register */
106 #define MV88E6XXX_G2_PVT_DATA 0x0c
107 #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f
108
109 /* Offset 0x0D: Switch MAC/WoL/WoF Register */
110 #define MV88E6XXX_G2_SWITCH_MAC 0x0d
111 #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000
112 #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00
113 #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff
114
115 /* Offset 0x0E: ATU Stats Register */
116 #define MV88E6XXX_G2_ATU_STATS 0x0e
117
118 /* Offset 0x0F: Priority Override Table */
119 #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f
120 #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000
121 #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000
122 #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00
123 #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080
124 #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030
125 #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008
126 #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007
127
128 /* Offset 0x14: EEPROM Command */
129 #define MV88E6XXX_G2_EEPROM_CMD 0x14
130 #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000
131 #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000
132 #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000
133 #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000
134 #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000
135 #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800
136 #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400
137 #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff
138 #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff
139
140 /* Offset 0x15: EEPROM Data */
141 #define MV88E6352_G2_EEPROM_DATA 0x15
142 #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff
143
144 /* Offset 0x15: EEPROM Addr */
145 #define MV88E6390_G2_EEPROM_ADDR 0x15
146 #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff
147
148 /* Offset 0x16: AVB Command Register */
149 #define MV88E6352_G2_AVB_CMD 0x16
150 #define MV88E6352_G2_AVB_CMD_BUSY 0x8000
151 #define MV88E6352_G2_AVB_CMD_OP_READ 0x4000
152 #define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000
153 #define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000
154 #define MV88E6390_G2_AVB_CMD_OP_READ 0x0000
155 #define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000
156 #define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000
157 #define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00
158 #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe
159 #define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
160 #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
161 #define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00
162 #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e
163 #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f
164 #define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0
165 #define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1
166 #define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2
167 #define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3
168 #define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0
169 #define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f
170
171 /* Offset 0x17: AVB Data Register */
172 #define MV88E6352_G2_AVB_DATA 0x17
173
174 /* Offset 0x18: SMI PHY Command Register */
175 #define MV88E6XXX_G2_SMI_PHY_CMD 0x18
176 #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000
177 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000
178 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000
179 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000
180 #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000
181 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000
182 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000
183 #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000
184 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00
185 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400
186 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800
187 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000
188 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400
189 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800
190 #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00
191 #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0
192 #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f
193 #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff
194
195 /* Offset 0x19: SMI PHY Data Register */
196 #define MV88E6XXX_G2_SMI_PHY_DATA 0x19
197
198 /* Offset 0x1A: Scratch and Misc. Register */
199 #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a
200 #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000
201 #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00
202 #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff
203
204 /* Offset 0x1B: Watch Dog Control Register */
205 #define MV88E6250_G2_WDOG_CTL 0x1b
206 #define MV88E6250_G2_WDOG_CTL_QC_HISTORY 0x0100
207 #define MV88E6250_G2_WDOG_CTL_QC_EVENT 0x0080
208 #define MV88E6250_G2_WDOG_CTL_QC_ENABLE 0x0040
209 #define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY 0x0020
210 #define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT 0x0010
211 #define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
212 #define MV88E6250_G2_WDOG_CTL_FORCE_IRQ 0x0004
213 #define MV88E6250_G2_WDOG_CTL_HISTORY 0x0002
214 #define MV88E6250_G2_WDOG_CTL_SWRESET 0x0001
215
216 /* Offset 0x1B: Watch Dog Control Register */
217 #define MV88E6352_G2_WDOG_CTL 0x1b
218 #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080
219 #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040
220 #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020
221 #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010
222 #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
223 #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004
224 #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002
225 #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001
226
227 /* Offset 0x1B: Watch Dog Control Register */
228 #define MV88E6390_G2_WDOG_CTL 0x1b
229 #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000
230 #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00
231 #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000
232 #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000
233 #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100
234 #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200
235 #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300
236 #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff
237 #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008
238 #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004
239 #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002
240 #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001
241
242 /* Offset 0x1C: QoS Weights Register */
243 #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c
244 #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000
245 #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00
246 #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00
247 #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff
248
249 /* Offset 0x1D: Misc Register */
250 #define MV88E6XXX_G2_MISC 0x1d
251 #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000
252 #define MV88E6352_G2_NOEGR_POLICY 0x2000
253 #define MV88E6390_G2_LAG_ID_4 0x2000
254
255 /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
256 /* Offset 0x02: Misc Configuration */
257 #define MV88E6352_G2_SCRATCH_MISC_CFG 0x02
258 #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80
259 /* Offset 0x60-0x61: GPIO Configuration */
260 #define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60
261 #define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61
262 /* Offset 0x62-0x63: GPIO Direction */
263 #define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62
264 #define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63
265 #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0
266 #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1
267 /* Offset 0x64-0x65: GPIO Data */
268 #define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64
269 #define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65
270 /* Offset 0x68-0x6F: GPIO Pin Control */
271 #define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68
272 #define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69
273 #define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A
274 #define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B
275 #define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C
276 #define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D
277 #define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E
278 #define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F
279 #define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70
280 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71
281 #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2)
282 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72
283 #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0x3
284
285 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0
286 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1
287 #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2
288
289 #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
290
mv88e6xxx_g2_require(struct mv88e6xxx_chip * chip)291 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
292 {
293 return 0;
294 }
295
296 int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
297 int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
298 int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg,
299 int bit, int val);
300
301 int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
302 int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
303
304 int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
305 struct mii_bus *bus,
306 int addr, int reg, u16 *val);
307 int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
308 struct mii_bus *bus,
309 int addr, int reg, u16 val);
310 int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
311
312 int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
313 struct ethtool_eeprom *eeprom, u8 *data);
314 int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
315 struct ethtool_eeprom *eeprom, u8 *data);
316
317 int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
318 struct ethtool_eeprom *eeprom, u8 *data);
319 int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
320 struct ethtool_eeprom *eeprom, u8 *data);
321
322 int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
323 int src_port, u16 data);
324 int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);
325
326 int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
327 void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
328
329 int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
330 struct mii_bus *bus);
331 void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
332 struct mii_bus *bus);
333
334 int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
335 int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
336
337 int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);
338
339 int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);
340
341 int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
342 int port);
343
344 extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
345 extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops;
346 extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
347
348 extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
349 extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
350 extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;
351
352 extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
353
354 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
355 bool external);
356
357 #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
358
mv88e6xxx_g2_require(struct mv88e6xxx_chip * chip)359 static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
360 {
361 if (chip->info->global2_addr) {
362 dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n");
363 return -EOPNOTSUPP;
364 }
365
366 return 0;
367 }
368
mv88e6xxx_g2_read(struct mv88e6xxx_chip * chip,int reg,u16 * val)369 static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
370 {
371 return -EOPNOTSUPP;
372 }
373
mv88e6xxx_g2_write(struct mv88e6xxx_chip * chip,int reg,u16 val)374 static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
375 {
376 return -EOPNOTSUPP;
377 }
378
mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip * chip,int reg,int bit,int val)379 static inline int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip,
380 int reg, int bit, int val)
381 {
382 return -EOPNOTSUPP;
383 }
384
mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip * chip,int port)385 static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip,
386 int port)
387 {
388 return -EOPNOTSUPP;
389 }
390
mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip * chip,int port)391 static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip,
392 int port)
393 {
394 return -EOPNOTSUPP;
395 }
396
mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip * chip,struct mii_bus * bus,int addr,int reg,u16 * val)397 static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
398 struct mii_bus *bus,
399 int addr, int reg, u16 *val)
400 {
401 return -EOPNOTSUPP;
402 }
403
mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip * chip,struct mii_bus * bus,int addr,int reg,u16 val)404 static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
405 struct mii_bus *bus,
406 int addr, int reg, u16 val)
407 {
408 return -EOPNOTSUPP;
409 }
410
mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip * chip,u8 * addr)411 static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip,
412 u8 *addr)
413 {
414 return -EOPNOTSUPP;
415 }
416
mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip * chip,struct ethtool_eeprom * eeprom,u8 * data)417 static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
418 struct ethtool_eeprom *eeprom,
419 u8 *data)
420 {
421 return -EOPNOTSUPP;
422 }
423
mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip * chip,struct ethtool_eeprom * eeprom,u8 * data)424 static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
425 struct ethtool_eeprom *eeprom,
426 u8 *data)
427 {
428 return -EOPNOTSUPP;
429 }
430
mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip * chip,struct ethtool_eeprom * eeprom,u8 * data)431 static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
432 struct ethtool_eeprom *eeprom,
433 u8 *data)
434 {
435 return -EOPNOTSUPP;
436 }
437
mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip * chip,struct ethtool_eeprom * eeprom,u8 * data)438 static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
439 struct ethtool_eeprom *eeprom,
440 u8 *data)
441 {
442 return -EOPNOTSUPP;
443 }
444
mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip * chip,int src_dev,int src_port,u16 data)445 static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip,
446 int src_dev, int src_port, u16 data)
447 {
448 return -EOPNOTSUPP;
449 }
450
mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip * chip)451 static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
452 {
453 return -EOPNOTSUPP;
454 }
455
mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip * chip)456 static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
457 {
458 return -EOPNOTSUPP;
459 }
460
mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip * chip)461 static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
462 {
463 }
464
mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip * chip,struct mii_bus * bus)465 static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
466 struct mii_bus *bus)
467 {
468 return 0;
469 }
470
mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip * chip,struct mii_bus * bus)471 static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
472 struct mii_bus *bus)
473 {
474 }
475
mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip * chip)476 static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
477 {
478 return -EOPNOTSUPP;
479 }
480
mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip * chip)481 static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
482 {
483 return -EOPNOTSUPP;
484 }
485
mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip * chip)486 static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
487 {
488 return -EOPNOTSUPP;
489 }
490
491 static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {};
492 static const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = {};
493 static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};
494
495 static const struct mv88e6xxx_avb_ops mv88e6165_avb_ops = {};
496 static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {};
497 static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {};
498
499 static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {};
500
mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip * chip,bool external)501 static inline int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
502 bool external)
503 {
504 return -EOPNOTSUPP;
505 }
506
mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip * chip)507 static inline int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
508 {
509 return -EOPNOTSUPP;
510 }
511
mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip * chip,int target,int port)512 static inline int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
513 int target, int port)
514 {
515 return -EOPNOTSUPP;
516 }
517
518 #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
519
520 #endif /* _MV88E6XXX_GLOBAL2_H */
521
