1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4 * Author: Rahul Sharma <rahul.sharma@samsung.com> 5 * 6 * Common Clock Framework support for Exynos5260 SoC. 7 */ 8 9 #ifndef __CLK_EXYNOS5260_H 10 #define __CLK_EXYNOS5260_H 11 12 /* 13 *Registers for CMU_AUD 14 */ 15 #define MUX_SEL_AUD 0x0200 16 #define MUX_ENABLE_AUD 0x0300 17 #define MUX_STAT_AUD 0x0400 18 #define MUX_IGNORE_AUD 0x0500 19 #define DIV_AUD0 0x0600 20 #define DIV_AUD1 0x0604 21 #define DIV_STAT_AUD0 0x0700 22 #define DIV_STAT_AUD1 0x0704 23 #define EN_ACLK_AUD 0x0800 24 #define EN_PCLK_AUD 0x0900 25 #define EN_SCLK_AUD 0x0a00 26 #define EN_IP_AUD 0x0b00 27 28 /* 29 *Registers for CMU_DISP 30 */ 31 #define MUX_SEL_DISP0 0x0200 32 #define MUX_SEL_DISP1 0x0204 33 #define MUX_SEL_DISP2 0x0208 34 #define MUX_SEL_DISP3 0x020C 35 #define MUX_SEL_DISP4 0x0210 36 #define MUX_ENABLE_DISP0 0x0300 37 #define MUX_ENABLE_DISP1 0x0304 38 #define MUX_ENABLE_DISP2 0x0308 39 #define MUX_ENABLE_DISP3 0x030c 40 #define MUX_ENABLE_DISP4 0x0310 41 #define MUX_STAT_DISP0 0x0400 42 #define MUX_STAT_DISP1 0x0404 43 #define MUX_STAT_DISP2 0x0408 44 #define MUX_STAT_DISP3 0x040c 45 #define MUX_STAT_DISP4 0x0410 46 #define MUX_IGNORE_DISP0 0x0500 47 #define MUX_IGNORE_DISP1 0x0504 48 #define MUX_IGNORE_DISP2 0x0508 49 #define MUX_IGNORE_DISP3 0x050c 50 #define MUX_IGNORE_DISP4 0x0510 51 #define DIV_DISP 0x0600 52 #define DIV_STAT_DISP 0x0700 53 #define EN_ACLK_DISP 0x0800 54 #define EN_PCLK_DISP 0x0900 55 #define EN_SCLK_DISP0 0x0a00 56 #define EN_SCLK_DISP1 0x0a04 57 #define EN_IP_DISP 0x0b00 58 #define EN_IP_DISP_BUS 0x0b04 59 60 61 /* 62 *Registers for CMU_EGL 63 */ 64 #define EGL_PLL_LOCK 0x0000 65 #define EGL_DPLL_LOCK 0x0004 66 #define EGL_PLL_CON0 0x0100 67 #define EGL_PLL_CON1 0x0104 68 #define EGL_PLL_FREQ_DET 0x010c 69 #define EGL_DPLL_CON0 0x0110 70 #define EGL_DPLL_CON1 0x0114 71 #define EGL_DPLL_FREQ_DET 0x011c 72 #define MUX_SEL_EGL 0x0200 73 #define MUX_ENABLE_EGL 0x0300 74 #define MUX_STAT_EGL 0x0400 75 #define DIV_EGL 0x0600 76 #define DIV_EGL_PLL_FDET 0x0604 77 #define DIV_STAT_EGL 0x0700 78 #define DIV_STAT_EGL_PLL_FDET 0x0704 79 #define EN_ACLK_EGL 0x0800 80 #define EN_PCLK_EGL 0x0900 81 #define EN_SCLK_EGL 0x0a00 82 #define EN_IP_EGL 0x0b00 83 #define CLKOUT_CMU_EGL 0x0c00 84 #define CLKOUT_CMU_EGL_DIV_STAT 0x0c04 85 #define ARMCLK_STOPCTRL 0x1000 86 #define EAGLE_EMA_CTRL 0x1008 87 #define EAGLE_EMA_STATUS 0x100c 88 #define PWR_CTRL 0x1020 89 #define PWR_CTRL2 0x1024 90 #define CLKSTOP_CTRL 0x1028 91 #define INTR_SPREAD_EN 0x1080 92 #define INTR_SPREAD_USE_STANDBYWFI 0x1084 93 #define INTR_SPREAD_BLOCKING_DURATION 0x1088 94 #define CMU_EGL_SPARE0 0x2000 95 #define CMU_EGL_SPARE1 0x2004 96 #define CMU_EGL_SPARE2 0x2008 97 #define CMU_EGL_SPARE3 0x200c 98 #define CMU_EGL_SPARE4 0x2010 99 100 /* 101 *Registers for CMU_FSYS 102 */ 103 104 #define MUX_SEL_FSYS0 0x0200 105 #define MUX_SEL_FSYS1 0x0204 106 #define MUX_ENABLE_FSYS0 0x0300 107 #define MUX_ENABLE_FSYS1 0x0304 108 #define MUX_STAT_FSYS0 0x0400 109 #define MUX_STAT_FSYS1 0x0404 110 #define MUX_IGNORE_FSYS0 0x0500 111 #define MUX_IGNORE_FSYS1 0x0504 112 #define EN_ACLK_FSYS 0x0800 113 #define EN_ACLK_FSYS_SECURE_RTIC 0x0804 114 #define EN_ACLK_FSYS_SECURE_SMMU_RTIC 0x0808 115 #define EN_PCLK_FSYS 0x0900 116 #define EN_SCLK_FSYS 0x0a00 117 #define EN_IP_FSYS 0x0b00 118 #define EN_IP_FSYS_SECURE_RTIC 0x0b04 119 #define EN_IP_FSYS_SECURE_SMMU_RTIC 0x0b08 120 121 /* 122 *Registers for CMU_G2D 123 */ 124 125 #define MUX_SEL_G2D 0x0200 126 #define MUX_ENABLE_G2D 0x0300 127 #define MUX_STAT_G2D 0x0400 128 #define DIV_G2D 0x0600 129 #define DIV_STAT_G2D 0x0700 130 #define EN_ACLK_G2D 0x0800 131 #define EN_ACLK_G2D_SECURE_SSS 0x0804 132 #define EN_ACLK_G2D_SECURE_SLIM_SSS 0x0808 133 #define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS 0x080c 134 #define EN_ACLK_G2D_SECURE_SMMU_SSS 0x0810 135 #define EN_ACLK_G2D_SECURE_SMMU_MDMA 0x0814 136 #define EN_ACLK_G2D_SECURE_SMMU_G2D 0x0818 137 #define EN_PCLK_G2D 0x0900 138 #define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS 0x0904 139 #define EN_PCLK_G2D_SECURE_SMMU_SSS 0x0908 140 #define EN_PCLK_G2D_SECURE_SMMU_MDMA 0x090c 141 #define EN_PCLK_G2D_SECURE_SMMU_G2D 0x0910 142 #define EN_IP_G2D 0x0b00 143 #define EN_IP_G2D_SECURE_SSS 0x0b04 144 #define EN_IP_G2D_SECURE_SLIM_SSS 0x0b08 145 #define EN_IP_G2D_SECURE_SMMU_SLIM_SSS 0x0b0c 146 #define EN_IP_G2D_SECURE_SMMU_SSS 0x0b10 147 #define EN_IP_G2D_SECURE_SMMU_MDMA 0x0b14 148 #define EN_IP_G2D_SECURE_SMMU_G2D 0x0b18 149 150 /* 151 *Registers for CMU_G3D 152 */ 153 154 #define G3D_PLL_LOCK 0x0000 155 #define G3D_PLL_CON0 0x0100 156 #define G3D_PLL_CON1 0x0104 157 #define G3D_PLL_FDET 0x010c 158 #define MUX_SEL_G3D 0x0200 159 #define MUX_EN_G3D 0x0300 160 #define MUX_STAT_G3D 0x0400 161 #define MUX_IGNORE_G3D 0x0500 162 #define DIV_G3D 0x0600 163 #define DIV_G3D_PLL_FDET 0x0604 164 #define DIV_STAT_G3D 0x0700 165 #define DIV_STAT_G3D_PLL_FDET 0x0704 166 #define EN_ACLK_G3D 0x0800 167 #define EN_PCLK_G3D 0x0900 168 #define EN_SCLK_G3D 0x0a00 169 #define EN_IP_G3D 0x0b00 170 #define CLKOUT_CMU_G3D 0x0c00 171 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 172 #define G3DCLK_STOPCTRL 0x1000 173 #define G3D_EMA_CTRL 0x1008 174 #define G3D_EMA_STATUS 0x100c 175 176 /* 177 *Registers for CMU_GSCL 178 */ 179 180 #define MUX_SEL_GSCL 0x0200 181 #define MUX_EN_GSCL 0x0300 182 #define MUX_STAT_GSCL 0x0400 183 #define MUX_IGNORE_GSCL 0x0500 184 #define DIV_GSCL 0x0600 185 #define DIV_STAT_GSCL 0x0700 186 #define EN_ACLK_GSCL 0x0800 187 #define EN_ACLK_GSCL_FIMC 0x0804 188 #define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0808 189 #define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 0x080c 190 #define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 0x0810 191 #define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 0x0814 192 #define EN_PCLK_GSCL 0x0900 193 #define EN_PCLK_GSCL_FIMC 0x0904 194 #define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0908 195 #define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 0x090c 196 #define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 0x0910 197 #define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 0x0914 198 #define EN_SCLK_GSCL 0x0a00 199 #define EN_SCLK_GSCL_FIMC 0x0a04 200 #define EN_IP_GSCL 0x0b00 201 #define EN_IP_GSCL_FIMC 0x0b04 202 #define EN_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 203 #define EN_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 204 #define EN_IP_GSCL_SECURE_SMMU_MSCL0 0x0b10 205 #define EN_IP_GSCL_SECURE_SMMU_MSCL1 0x0b14 206 207 /* 208 *Registers for CMU_ISP 209 */ 210 #define MUX_SEL_ISP0 0x0200 211 #define MUX_SEL_ISP1 0x0204 212 #define MUX_ENABLE_ISP0 0x0300 213 #define MUX_ENABLE_ISP1 0x0304 214 #define MUX_STAT_ISP0 0x0400 215 #define MUX_STAT_ISP1 0x0404 216 #define MUX_IGNORE_ISP0 0x0500 217 #define MUX_IGNORE_ISP1 0x0504 218 #define DIV_ISP 0x0600 219 #define DIV_STAT_ISP 0x0700 220 #define EN_ACLK_ISP0 0x0800 221 #define EN_ACLK_ISP1 0x0804 222 #define EN_PCLK_ISP0 0x0900 223 #define EN_PCLK_ISP1 0x0904 224 #define EN_SCLK_ISP 0x0a00 225 #define EN_IP_ISP0 0x0b00 226 #define EN_IP_ISP1 0x0b04 227 228 /* 229 *Registers for CMU_KFC 230 */ 231 #define KFC_PLL_LOCK 0x0000 232 #define KFC_PLL_CON0 0x0100 233 #define KFC_PLL_CON1 0x0104 234 #define KFC_PLL_FDET 0x010c 235 #define MUX_SEL_KFC0 0x0200 236 #define MUX_SEL_KFC2 0x0208 237 #define MUX_ENABLE_KFC0 0x0300 238 #define MUX_ENABLE_KFC2 0x0308 239 #define MUX_STAT_KFC0 0x0400 240 #define MUX_STAT_KFC2 0x0408 241 #define DIV_KFC 0x0600 242 #define DIV_KFC_PLL_FDET 0x0604 243 #define DIV_STAT_KFC 0x0700 244 #define DIV_STAT_KFC_PLL_FDET 0x0704 245 #define EN_ACLK_KFC 0x0800 246 #define EN_PCLK_KFC 0x0900 247 #define EN_SCLK_KFC 0x0a00 248 #define EN_IP_KFC 0x0b00 249 #define CLKOUT_CMU_KFC 0x0c00 250 #define CLKOUT_CMU_KFC_DIV_STAT 0x0c04 251 #define ARMCLK_STOPCTRL_KFC 0x1000 252 #define ARM_EMA_CTRL 0x1008 253 #define ARM_EMA_STATUS 0x100c 254 #define PWR_CTRL_KFC 0x1020 255 #define PWR_CTRL2_KFC 0x1024 256 #define CLKSTOP_CTRL_KFC 0x1028 257 #define INTR_SPREAD_ENABLE_KFC 0x1080 258 #define INTR_SPREAD_USE_STANDBYWFI_KFC 0x1084 259 #define INTR_SPREAD_BLOCKING_DURATION_KFC 0x1088 260 #define CMU_KFC_SPARE0 0x2000 261 #define CMU_KFC_SPARE1 0x2004 262 #define CMU_KFC_SPARE2 0x2008 263 #define CMU_KFC_SPARE3 0x200c 264 #define CMU_KFC_SPARE4 0x2010 265 266 /* 267 *Registers for CMU_MFC 268 */ 269 #define MUX_SEL_MFC 0x0200 270 #define MUX_ENABLE_MFC 0x0300 271 #define MUX_STAT_MFC 0x0400 272 #define DIV_MFC 0x0600 273 #define DIV_STAT_MFC 0x0700 274 #define EN_ACLK_MFC 0x0800 275 #define EN_ACLK_SECURE_SMMU2_MFC 0x0804 276 #define EN_PCLK_MFC 0x0900 277 #define EN_PCLK_SECURE_SMMU2_MFC 0x0904 278 #define EN_IP_MFC 0x0b00 279 #define EN_IP_MFC_SECURE_SMMU2_MFC 0x0b04 280 281 /* 282 *Registers for CMU_MIF 283 */ 284 #define MEM_PLL_LOCK 0x0000 285 #define BUS_PLL_LOCK 0x0004 286 #define MEDIA_PLL_LOCK 0x0008 287 #define MEM_PLL_CON0 0x0100 288 #define MEM_PLL_CON1 0x0104 289 #define MEM_PLL_FDET 0x010c 290 #define BUS_PLL_CON0 0x0110 291 #define BUS_PLL_CON1 0x0114 292 #define BUS_PLL_FDET 0x011c 293 #define MEDIA_PLL_CON0 0x0120 294 #define MEDIA_PLL_CON1 0x0124 295 #define MEDIA_PLL_FDET 0x012c 296 #define MUX_SEL_MIF 0x0200 297 #define MUX_ENABLE_MIF 0x0300 298 #define MUX_STAT_MIF 0x0400 299 #define MUX_IGNORE_MIF 0x0500 300 #define DIV_MIF 0x0600 301 #define DIV_MIF_PLL_FDET 0x0604 302 #define DIV_STAT_MIF 0x0700 303 #define DIV_STAT_MIF_PLL_FDET 0x0704 304 #define EN_ACLK_MIF 0x0800 305 #define EN_ACLK_MIF_SECURE_DREX1_TZ 0x0804 306 #define EN_ACLK_MIF_SECURE_DREX0_TZ 0x0808 307 #define EN_ACLK_MIF_SECURE_INTMEM 0x080c 308 #define EN_PCLK_MIF 0x0900 309 #define EN_PCLK_MIF_SECURE_MONOCNT 0x0904 310 #define EN_PCLK_MIF_SECURE_RTC_APBIF 0x0908 311 #define EN_PCLK_MIF_SECURE_DREX1_TZ 0x090c 312 #define EN_PCLK_MIF_SECURE_DREX0_TZ 0x0910 313 #define EN_SCLK_MIF 0x0a00 314 #define EN_IP_MIF 0x0b00 315 #define EN_IP_MIF_SECURE_MONOCNT 0x0b04 316 #define EN_IP_MIF_SECURE_RTC_APBIF 0x0b08 317 #define EN_IP_MIF_SECURE_DREX1_TZ 0x0b0c 318 #define EN_IP_MIF_SECURE_DREX0_TZ 0x0b10 319 #define EN_IP_MIF_SECURE_INTEMEM 0x0b14 320 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 321 #define DREX_FREQ_CTRL 0x1000 322 #define PAUSE 0x1004 323 #define DDRPHY_LOCK_CTRL 0x1008 324 #define CLKOUT_CMU_MIF 0xcb00 325 326 /* 327 *Registers for CMU_PERI 328 */ 329 #define MUX_SEL_PERI 0x0200 330 #define MUX_SEL_PERI1 0x0204 331 #define MUX_ENABLE_PERI 0x0300 332 #define MUX_ENABLE_PERI1 0x0304 333 #define MUX_STAT_PERI 0x0400 334 #define MUX_STAT_PERI1 0x0404 335 #define MUX_IGNORE_PERI 0x0500 336 #define MUX_IGNORE_PERI1 0x0504 337 #define DIV_PERI 0x0600 338 #define DIV_STAT_PERI 0x0700 339 #define EN_PCLK_PERI0 0x0800 340 #define EN_PCLK_PERI1 0x0804 341 #define EN_PCLK_PERI2 0x0808 342 #define EN_PCLK_PERI3 0x080c 343 #define EN_PCLK_PERI_SECURE_CHIPID 0x0810 344 #define EN_PCLK_PERI_SECURE_PROVKEY0 0x0814 345 #define EN_PCLK_PERI_SECURE_PROVKEY1 0x0818 346 #define EN_PCLK_PERI_SECURE_SECKEY 0x081c 347 #define EN_PCLK_PERI_SECURE_ANTIRBKCNT 0x0820 348 #define EN_PCLK_PERI_SECURE_TOP_RTC 0x0824 349 #define EN_PCLK_PERI_SECURE_TZPC 0x0828 350 #define EN_SCLK_PERI 0x0a00 351 #define EN_SCLK_PERI_SECURE_TOP_RTC 0x0a04 352 #define EN_IP_PERI0 0x0b00 353 #define EN_IP_PERI1 0x0b04 354 #define EN_IP_PERI2 0x0b08 355 #define EN_IP_PERI_SECURE_CHIPID 0x0b0c 356 #define EN_IP_PERI_SECURE_PROVKEY0 0x0b10 357 #define EN_IP_PERI_SECURE_PROVKEY1 0x0b14 358 #define EN_IP_PERI_SECURE_SECKEY 0x0b18 359 #define EN_IP_PERI_SECURE_ANTIRBKCNT 0x0b1c 360 #define EN_IP_PERI_SECURE_TOP_RTC 0x0b20 361 #define EN_IP_PERI_SECURE_TZPC 0x0b24 362 363 /* 364 *Registers for CMU_TOP 365 */ 366 #define DISP_PLL_LOCK 0x0000 367 #define AUD_PLL_LOCK 0x0004 368 #define DISP_PLL_CON0 0x0100 369 #define DISP_PLL_CON1 0x0104 370 #define DISP_PLL_FDET 0x0108 371 #define AUD_PLL_CON0 0x0110 372 #define AUD_PLL_CON1 0x0114 373 #define AUD_PLL_CON2 0x0118 374 #define AUD_PLL_FDET 0x011c 375 #define MUX_SEL_TOP_PLL0 0x0200 376 #define MUX_SEL_TOP_MFC 0x0204 377 #define MUX_SEL_TOP_G2D 0x0208 378 #define MUX_SEL_TOP_GSCL 0x020c 379 #define MUX_SEL_TOP_ISP10 0x0214 380 #define MUX_SEL_TOP_ISP11 0x0218 381 #define MUX_SEL_TOP_DISP0 0x021c 382 #define MUX_SEL_TOP_DISP1 0x0220 383 #define MUX_SEL_TOP_BUS 0x0224 384 #define MUX_SEL_TOP_PERI0 0x0228 385 #define MUX_SEL_TOP_PERI1 0x022c 386 #define MUX_SEL_TOP_FSYS 0x0230 387 #define MUX_ENABLE_TOP_PLL0 0x0300 388 #define MUX_ENABLE_TOP_MFC 0x0304 389 #define MUX_ENABLE_TOP_G2D 0x0308 390 #define MUX_ENABLE_TOP_GSCL 0x030c 391 #define MUX_ENABLE_TOP_ISP10 0x0314 392 #define MUX_ENABLE_TOP_ISP11 0x0318 393 #define MUX_ENABLE_TOP_DISP0 0x031c 394 #define MUX_ENABLE_TOP_DISP1 0x0320 395 #define MUX_ENABLE_TOP_BUS 0x0324 396 #define MUX_ENABLE_TOP_PERI0 0x0328 397 #define MUX_ENABLE_TOP_PERI1 0x032c 398 #define MUX_ENABLE_TOP_FSYS 0x0330 399 #define MUX_STAT_TOP_PLL0 0x0400 400 #define MUX_STAT_TOP_MFC 0x0404 401 #define MUX_STAT_TOP_G2D 0x0408 402 #define MUX_STAT_TOP_GSCL 0x040c 403 #define MUX_STAT_TOP_ISP10 0x0414 404 #define MUX_STAT_TOP_ISP11 0x0418 405 #define MUX_STAT_TOP_DISP0 0x041c 406 #define MUX_STAT_TOP_DISP1 0x0420 407 #define MUX_STAT_TOP_BUS 0x0424 408 #define MUX_STAT_TOP_PERI0 0x0428 409 #define MUX_STAT_TOP_PERI1 0x042c 410 #define MUX_STAT_TOP_FSYS 0x0430 411 #define MUX_IGNORE_TOP_PLL0 0x0500 412 #define MUX_IGNORE_TOP_MFC 0x0504 413 #define MUX_IGNORE_TOP_G2D 0x0508 414 #define MUX_IGNORE_TOP_GSCL 0x050c 415 #define MUX_IGNORE_TOP_ISP10 0x0514 416 #define MUX_IGNORE_TOP_ISP11 0x0518 417 #define MUX_IGNORE_TOP_DISP0 0x051c 418 #define MUX_IGNORE_TOP_DISP1 0x0520 419 #define MUX_IGNORE_TOP_BUS 0x0524 420 #define MUX_IGNORE_TOP_PERI0 0x0528 421 #define MUX_IGNORE_TOP_PERI1 0x052c 422 #define MUX_IGNORE_TOP_FSYS 0x0530 423 #define DIV_TOP_G2D_MFC 0x0600 424 #define DIV_TOP_GSCL_ISP0 0x0604 425 #define DIV_TOP_ISP10 0x0608 426 #define DIV_TOP_ISP11 0x060c 427 #define DIV_TOP_DISP 0x0610 428 #define DIV_TOP_BUS 0x0614 429 #define DIV_TOP_PERI0 0x0618 430 #define DIV_TOP_PERI1 0x061c 431 #define DIV_TOP_PERI2 0x0620 432 #define DIV_TOP_FSYS0 0x0624 433 #define DIV_TOP_FSYS1 0x0628 434 #define DIV_TOP_HPM 0x062c 435 #define DIV_TOP_PLL_FDET 0x0630 436 #define DIV_STAT_TOP_G2D_MFC 0x0700 437 #define DIV_STAT_TOP_GSCL_ISP0 0x0704 438 #define DIV_STAT_TOP_ISP10 0x0708 439 #define DIV_STAT_TOP_ISP11 0x070c 440 #define DIV_STAT_TOP_DISP 0x0710 441 #define DIV_STAT_TOP_BUS 0x0714 442 #define DIV_STAT_TOP_PERI0 0x0718 443 #define DIV_STAT_TOP_PERI1 0x071c 444 #define DIV_STAT_TOP_PERI2 0x0720 445 #define DIV_STAT_TOP_FSYS0 0x0724 446 #define DIV_STAT_TOP_FSYS1 0x0728 447 #define DIV_STAT_TOP_HPM 0x072c 448 #define DIV_STAT_TOP_PLL_FDET 0x0730 449 #define EN_ACLK_TOP 0x0800 450 #define EN_SCLK_TOP 0x0a00 451 #define EN_IP_TOP 0x0b00 452 #define CLKOUT_CMU_TOP 0x0c00 453 #define CLKOUT_CMU_TOP_DIV_STAT 0x0c04 454 455 #endif /*__CLK_EXYNOS5260_H */ 456 457
