1 /* SPDX-License-Identifier: ISC */
2 /*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
5 */
6
7 #ifndef __MT76X02_MAC_H
8 #define __MT76X02_MAC_H
9
10 struct mt76x02_dev;
11
12 struct mt76x02_tx_status {
13 u8 valid:1;
14 u8 success:1;
15 u8 aggr:1;
16 u8 ack_req:1;
17 u8 wcid;
18 u8 pktid;
19 u8 retry;
20 u16 rate;
21 } __packed __aligned(2);
22
23 #define MT_VIF_WCID(_n) (254 - ((_n) & 7))
24 #define MT_MAX_VIFS 8
25
26 struct mt76x02_vif {
27 struct mt76_wcid group_wcid; /* must be first */
28 u8 idx;
29 };
30
31 struct mt76x02_sta {
32 struct mt76_wcid wcid; /* must be first */
33
34 struct mt76x02_vif *vif;
35 struct mt76x02_tx_status status;
36 int n_frames;
37
38 };
39
40 #define MT_RXINFO_BA BIT(0)
41 #define MT_RXINFO_DATA BIT(1)
42 #define MT_RXINFO_NULL BIT(2)
43 #define MT_RXINFO_FRAG BIT(3)
44 #define MT_RXINFO_UNICAST BIT(4)
45 #define MT_RXINFO_MULTICAST BIT(5)
46 #define MT_RXINFO_BROADCAST BIT(6)
47 #define MT_RXINFO_MYBSS BIT(7)
48 #define MT_RXINFO_CRCERR BIT(8)
49 #define MT_RXINFO_ICVERR BIT(9)
50 #define MT_RXINFO_MICERR BIT(10)
51 #define MT_RXINFO_AMSDU BIT(11)
52 #define MT_RXINFO_HTC BIT(12)
53 #define MT_RXINFO_RSSI BIT(13)
54 #define MT_RXINFO_L2PAD BIT(14)
55 #define MT_RXINFO_AMPDU BIT(15)
56 #define MT_RXINFO_DECRYPT BIT(16)
57 #define MT_RXINFO_BSSIDX3 BIT(17)
58 #define MT_RXINFO_WAPI_KEY BIT(18)
59 #define MT_RXINFO_PN_LEN GENMASK(21, 19)
60 #define MT_RXINFO_SW_FTYPE0 BIT(22)
61 #define MT_RXINFO_SW_FTYPE1 BIT(23)
62 #define MT_RXINFO_PROBE_RESP BIT(24)
63 #define MT_RXINFO_BEACON BIT(25)
64 #define MT_RXINFO_DISASSOC BIT(26)
65 #define MT_RXINFO_DEAUTH BIT(27)
66 #define MT_RXINFO_ACTION BIT(28)
67 #define MT_RXINFO_TCP_SUM_ERR BIT(30)
68 #define MT_RXINFO_IP_SUM_ERR BIT(31)
69
70 #define MT_RXWI_CTL_WCID GENMASK(7, 0)
71 #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)
72 #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)
73 #define MT_RXWI_CTL_UDF GENMASK(15, 13)
74 #define MT_RXWI_CTL_MPDU_LEN GENMASK(29, 16)
75 #define MT_RXWI_CTL_EOF BIT(31)
76
77 #define MT_RXWI_TID GENMASK(3, 0)
78 #define MT_RXWI_SN GENMASK(15, 4)
79
80 #define MT_RXWI_RATE_INDEX GENMASK(5, 0)
81 #define MT_RXWI_RATE_LDPC BIT(6)
82 #define MT_RXWI_RATE_BW GENMASK(8, 7)
83 #define MT_RXWI_RATE_SGI BIT(9)
84 #define MT_RXWI_RATE_STBC BIT(10)
85 #define MT_RXWI_RATE_LDPC_EXSYM BIT(11)
86 #define MT_RXWI_RATE_PHY GENMASK(15, 13)
87
88 #define MT_RATE_INDEX_VHT_IDX GENMASK(3, 0)
89 #define MT_RATE_INDEX_VHT_NSS GENMASK(5, 4)
90
91 struct mt76x02_rxwi {
92 __le32 rxinfo;
93
94 __le32 ctl;
95
96 __le16 tid_sn;
97 __le16 rate;
98
99 u8 rssi[4];
100
101 __le32 bbp_rxinfo[4];
102 };
103
104 #define MT_TX_PWR_ADJ GENMASK(3, 0)
105
106 enum mt76x2_phy_bandwidth {
107 MT_PHY_BW_20,
108 MT_PHY_BW_40,
109 MT_PHY_BW_80,
110 };
111
112 #define MT_TXWI_FLAGS_FRAG BIT(0)
113 #define MT_TXWI_FLAGS_MMPS BIT(1)
114 #define MT_TXWI_FLAGS_CFACK BIT(2)
115 #define MT_TXWI_FLAGS_TS BIT(3)
116 #define MT_TXWI_FLAGS_AMPDU BIT(4)
117 #define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5)
118 #define MT_TXWI_FLAGS_TXOP GENMASK(9, 8)
119 #define MT_TXWI_FLAGS_NDPS BIT(10)
120 #define MT_TXWI_FLAGS_RTSBWSIG BIT(11)
121 #define MT_TXWI_FLAGS_NDP_BW GENMASK(13, 12)
122 #define MT_TXWI_FLAGS_SOUND BIT(14)
123 #define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15)
124
125 #define MT_TXWI_ACK_CTL_REQ BIT(0)
126 #define MT_TXWI_ACK_CTL_NSEQ BIT(1)
127 #define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2)
128
129 struct mt76x02_txwi {
130 __le16 flags;
131 __le16 rate;
132 u8 ack_ctl;
133 u8 wcid;
134 __le16 len_ctl;
135 __le32 iv;
136 __le32 eiv;
137 u8 aid;
138 u8 txstream;
139 u8 ctl2;
140 u8 pktid;
141 } __packed __aligned(4);
142
mt76x02_wait_for_mac(struct mt76_dev * dev)143 static inline bool mt76x02_wait_for_mac(struct mt76_dev *dev)
144 {
145 const u32 MAC_CSR0 = 0x1000;
146 int i;
147
148 for (i = 0; i < 500; i++) {
149 if (test_bit(MT76_REMOVED, &dev->state))
150 return false;
151
152 switch (dev->bus->rr(dev, MAC_CSR0)) {
153 case 0:
154 case ~0:
155 break;
156 default:
157 return true;
158 }
159 usleep_range(5000, 10000);
160 }
161 return false;
162 }
163
164 void mt76x02_mac_set_short_preamble(struct mt76x02_dev *dev, bool enable);
165 int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx,
166 u8 key_idx, struct ieee80211_key_conf *key);
167 int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx,
168 struct ieee80211_key_conf *key);
169 void mt76x02_mac_wcid_sync_pn(struct mt76x02_dev *dev, u8 idx,
170 struct ieee80211_key_conf *key);
171 void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, u8 vif_idx,
172 u8 *mac);
173 void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop);
174 void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid,
175 const struct ieee80211_tx_rate *rate);
176 bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev,
177 struct mt76x02_tx_status *stat);
178 void mt76x02_send_tx_status(struct mt76x02_dev *dev,
179 struct mt76x02_tx_status *stat, u8 *update);
180 int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb,
181 void *rxi);
182 void mt76x02_mac_set_tx_protection(struct mt76x02_dev *dev, bool legacy_prot,
183 int ht_mode);
184 void mt76x02_mac_set_rts_thresh(struct mt76x02_dev *dev, u32 val);
185 void mt76x02_mac_setaddr(struct mt76x02_dev *dev, const u8 *addr);
186 void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi,
187 struct sk_buff *skb, struct mt76_wcid *wcid,
188 struct ieee80211_sta *sta, int len);
189 void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq);
190 void mt76x02_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
191 struct mt76_queue_entry *e);
192 void mt76x02_update_channel(struct mt76_dev *mdev);
193 void mt76x02_mac_work(struct work_struct *work);
194
195 void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr);
196 int mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 vif_idx,
197 struct sk_buff *skb);
198 void mt76x02_mac_set_beacon_enable(struct mt76x02_dev *dev,
199 struct ieee80211_vif *vif, bool enable);
200
201 void mt76x02_edcca_init(struct mt76x02_dev *dev);
202 #endif
203
